###############################################################################
# #
# IAR Assembler V5.30.1.50284/W32 for MSP430 28/Apr/2012 03:06:22 #
# Copyright 1996-2011 IAR Systems AB. #
# #
# Target option = MSP430 #
# Source file = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\4e-infoBG2553.s43#
# List file = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\List\4e-infoBG2553.lst#
# Object file = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\Obj\4e-infoBG2553.r43#
# Command line = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\4e-infoBG2553.s43 #
# -OC:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\Obj\ #
# -s+ -M<> -w+ #
# -LC:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\List\ #
# -i -t8 -xD -r -D__MSP430G2553__ #
# -IC:\Programme\IAR Systems\Embedded Workbench 6.0 Kickstart\430\INC\ #
# #
###############################################################################
1 000000 ; ----------------------------------------------
------------------------
2 000000 ; 4e4th is a Forth based on CamelForth
3 000000 ; for the Texas Instruments MSP430
4 000000 ;
5 000000 ; This program is free software; you can
redistribute it and/or modify
6 000000 ; it under the terms of the GNU General Public
License as published by
7 000000 ; the Free Software Foundation; either version 3
of the License, or
8 000000 ; (at your option) any later version.
9 000000 ;
10 000000 ; This program is distributed in the hope that
it will be useful,
11 000000 ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 000000 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 000000 ; GNU General Public License for more details.
14 000000 ;
15 000000 ; You should have received a copy of the GNU
General Public License
16 000000 ; along with this program. If not, see
.
17 000000 ;
18 000000 ; See LICENSE TERMS in Brads file readme.txt as
well.
19 000000
20 000000 ; ----------------------------------------------
------------------------
21 000000 ; 4e-infoBG2553.s43 - user area is saved to
infoB - MSP430G2553
22 000000 ; ----------------------------------------------
------------------------
23 000000
24 000000 #include "msp430.h" ;
#define controlled include file
1 000000 /***********************************************
********************
2 000000 *
*
3 000000 * This file is a generic include file controlled
by *
4 000000 * compiler/assembler IDE generated defines
*
5 000000 *
*
6 000000 ************************************************
*******************/
7 000000
8 000000 #ifndef __msp430
9 000000 #define __msp430
10 000000
11 000000 #ifndef _SYSTEM_BUILD
12 000000 #pragma system_include
13 000000 #endif
14 000000
15 000000 #if defined (__MSP430C111__)
16 000000 #include "msp430c111.h"
18 000000 #elif defined (__MSP430C1111__)
19 000000 #include "msp430c1111.h"
21 000000 #elif defined (__MSP430C112__)
22 000000 #include "msp430c112.h"
24 000000 #elif defined (__MSP430C1121__)
25 000000 #include "msp430c1121.h"
27 000000 #elif defined (__MSP430C1331__)
28 000000 #include "msp430c1331.h"
30 000000 #elif defined (__MSP430C1351__)
31 000000 #include "msp430c1351.h"
33 000000 #elif defined (__MSP430C311S__)
34 000000 #include "msp430c311s.h"
36 000000 #elif defined (__MSP430C312__)
37 000000 #include "msp430c312.h"
39 000000 #elif defined (__MSP430C313__)
40 000000 #include "msp430c313.h"
42 000000 #elif defined (__MSP430C314__)
43 000000 #include "msp430c314.h"
45 000000 #elif defined (__MSP430C315__)
46 000000 #include "msp430c315.h"
48 000000 #elif defined (__MSP430C323__)
49 000000 #include "msp430c323.h"
51 000000 #elif defined (__MSP430C325__)
52 000000 #include "msp430c325.h"
54 000000 #elif defined (__MSP430C336__)
55 000000 #include "msp430c336.h"
57 000000 #elif defined (__MSP430C337__)
58 000000 #include "msp430c337.h"
60 000000 #elif defined (__MSP430C412__)
61 000000 #include "msp430c412.h"
63 000000 #elif defined (__MSP430C413__)
64 000000 #include "msp430c413.h"
66 000000 #elif defined (__MSP430CG4616__)
67 000000 #include "msp430cg4616.h"
69 000000 #elif defined (__MSP430CG4617__)
70 000000 #include "msp430cg4617.h"
72 000000 #elif defined (__MSP430CG4618__)
73 000000 #include "msp430cg4618.h"
75 000000 #elif defined (__MSP430CG4619__)
76 000000 #include "msp430cg4619.h"
78 000000 #elif defined (__MSP430E112__)
79 000000 #include "msp430e112.h"
81 000000 #elif defined (__MSP430E313__)
82 000000 #include "msp430e313.h"
84 000000 #elif defined (__MSP430E315__)
85 000000 #include "msp430e315.h"
87 000000 #elif defined (__MSP430E325__)
88 000000 #include "msp430e325.h"
90 000000 #elif defined (__MSP430E337__)
91 000000 #include "msp430e337.h"
93 000000 #elif defined (__MSP430F110__)
94 000000 #include "msp430f110.h"
96 000000 #elif defined (__MSP430F1101__)
97 000000 #include "msp430f1101.h"
99 000000 #elif defined (__MSP430F1101A__)
100 000000 #include "msp430f1101a.h"
102 000000 #elif defined (__MSP430F1111__)
103 000000 #include "msp430f1111.h"
105 000000 #elif defined (__MSP430F1111A__)
106 000000 #include "msp430f1111a.h"
108 000000 #elif defined (__MSP430F112__)
109 000000 #include "msp430f112.h"
111 000000 #elif defined (__MSP430F1121__)
112 000000 #include "msp430f1121.h"
114 000000 #elif defined (__MSP430F1121A__)
115 000000 #include "msp430f1121a.h"
117 000000 #elif defined (__MSP430F1122__)
118 000000 #include "msp430f1122.h"
120 000000 #elif defined (__MSP430F1132__)
121 000000 #include "msp430f1132.h"
123 000000 #elif defined (__MSP430F122__)
124 000000 #include "msp430f122.h"
126 000000 #elif defined (__MSP430F1222__)
127 000000 #include "msp430f1222.h"
129 000000 #elif defined (__MSP430F123__)
130 000000 #include "msp430f123.h"
132 000000 #elif defined (__MSP430F1232__)
133 000000 #include "msp430f1232.h"
135 000000 #elif defined (__MSP430F133__)
136 000000 #include "msp430f133.h"
138 000000 #elif defined (__MSP430F135__)
139 000000 #include "msp430f135.h"
141 000000 #elif defined (__MSP430F147__)
142 000000 #include "msp430f147.h"
144 000000 #elif defined (__MSP430F148__)
145 000000 #include "msp430f148.h"
147 000000 #elif defined (__MSP430F149__)
148 000000 #include "msp430f149.h"
150 000000 #elif defined (__MSP430F1471__)
151 000000 #include "msp430f1471.h"
153 000000 #elif defined (__MSP430F1481__)
154 000000 #include "msp430f1481.h"
156 000000 #elif defined (__MSP430F1491__)
157 000000 #include "msp430f1491.h"
159 000000 #elif defined (__MSP430F155__)
160 000000 #include "msp430f155.h"
162 000000 #elif defined (__MSP430F156__)
163 000000 #include "msp430f156.h"
165 000000 #elif defined (__MSP430F157__)
166 000000 #include "msp430f157.h"
168 000000 #elif defined (__MSP430F167__)
169 000000 #include "msp430f167.h"
171 000000 #elif defined (__MSP430F168__)
172 000000 #include "msp430f168.h"
174 000000 #elif defined (__MSP430F169__)
175 000000 #include "msp430f169.h"
177 000000 #elif defined (__MSP430F1610__)
178 000000 #include "msp430f1610.h"
180 000000 #elif defined (__MSP430F1611__)
181 000000 #include "msp430f1611.h"
183 000000 #elif defined (__MSP430F1612__)
184 000000 #include "msp430f1612.h"
186 000000 #elif defined (__MSP430F2001__)
187 000000 #include "msp430f2001.h"
189 000000 #elif defined (__MSP430F2011__)
190 000000 #include "msp430f2011.h"
192 000000 #elif defined (__MSP430F2002__)
193 000000 #include "msp430f2002.h"
195 000000 #elif defined (__MSP430F2012__)
196 000000 #include "msp430f2012.h"
198 000000 #elif defined (__MSP430F2003__)
199 000000 #include "msp430f2003.h"
201 000000 #elif defined (__MSP430F2013__)
202 000000 #include "msp430f2013.h"
204 000000 #elif defined (__MSP430F2101__)
205 000000 #include "msp430f2101.h"
207 000000 #elif defined (__MSP430F2111__)
208 000000 #include "msp430f2111.h"
210 000000 #elif defined (__MSP430F2121__)
211 000000 #include "msp430f2121.h"
213 000000 #elif defined (__MSP430F2131__)
214 000000 #include "msp430f2131.h"
216 000000 #elif defined (__MSP430F2112__)
217 000000 #include "msp430f2112.h"
219 000000 #elif defined (__MSP430F2122__)
220 000000 #include "msp430f2122.h"
222 000000 #elif defined (__MSP430F2132__)
223 000000 #include "msp430f2132.h"
225 000000 #elif defined (__MSP430F2232__)
226 000000 #include "msp430f2232.h"
228 000000 #elif defined (__MSP430F2252__)
229 000000 #include "msp430f2252.h"
231 000000 #elif defined (__MSP430F2272__)
232 000000 #include "msp430f2272.h"
234 000000 #elif defined (__MSP430F2234__)
235 000000 #include "msp430f2234.h"
237 000000 #elif defined (__MSP430F2254__)
238 000000 #include "msp430f2254.h"
240 000000 #elif defined (__MSP430F2274__)
241 000000 #include "msp430f2274.h"
243 000000 #elif defined (__MSP430F2330__)
244 000000 #include "msp430f2330.h"
246 000000 #elif defined (__MSP430F2350__)
247 000000 #include "msp430f2350.h"
249 000000 #elif defined (__MSP430F2370__)
250 000000 #include "msp430f2370.h"
252 000000 #elif defined (__MSP430F233__)
253 000000 #include "msp430f233.h"
255 000000 #elif defined (__MSP430F235__)
256 000000 #include "msp430f235.h"
258 000000 #elif defined (__MSP430F247__)
259 000000 #include "msp430f247.h"
261 000000 #elif defined (__MSP430F248__)
262 000000 #include "msp430f248.h"
264 000000 #elif defined (__MSP430F249__)
265 000000 #include "msp430f249.h"
267 000000 #elif defined (__MSP430F2410__)
268 000000 #include "msp430f2410.h"
270 000000 #elif defined (__MSP430F2471__)
271 000000 #include "msp430f2471.h"
273 000000 #elif defined (__MSP430F2481__)
274 000000 #include "msp430f2481.h"
276 000000 #elif defined (__MSP430F2491__)
277 000000 #include "msp430f2491.h"
279 000000 #elif defined (__MSP430F2416__)
280 000000 #include "msp430f2416.h"
282 000000 #elif defined (__MSP430F2417__)
283 000000 #include "msp430f2417.h"
285 000000 #elif defined (__MSP430F2418__)
286 000000 #include "msp430f2418.h"
288 000000 #elif defined (__MSP430F2419__)
289 000000 #include "msp430f2419.h"
291 000000 #elif defined (__MSP430F2616__)
292 000000 #include "msp430f2616.h"
294 000000 #elif defined (__MSP430F2617__)
295 000000 #include "msp430f2617.h"
297 000000 #elif defined (__MSP430F2618__)
298 000000 #include "msp430f2618.h"
300 000000 #elif defined (__MSP430F2619__)
301 000000 #include "msp430f2619.h"
303 000000 #elif defined (__MSP430F412__)
304 000000 #include "msp430f412.h"
306 000000 #elif defined (__MSP430F413__)
307 000000 #include "msp430f413.h"
309 000000 #elif defined (__MSP430F415__)
310 000000 #include "msp430f415.h"
312 000000 #elif defined (__MSP430F417__)
313 000000 #include "msp430f417.h"
315 000000 #elif defined (__MSP430F4132__)
316 000000 #include "msp430f4132.h"
318 000000 #elif defined (__MSP430F4152__)
319 000000 #include "msp430f4152.h"
321 000000 #elif defined (__MSP430F423__)
322 000000 #include "msp430f423.h"
324 000000 #elif defined (__MSP430F425__)
325 000000 #include "msp430f425.h"
327 000000 #elif defined (__MSP430F427__)
328 000000 #include "msp430f427.h"
330 000000 #elif defined (__MSP430F423A__)
331 000000 #include "msp430f423a.h"
333 000000 #elif defined (__MSP430F425A__)
334 000000 #include "msp430f425a.h"
336 000000 #elif defined (__MSP430F427A__)
337 000000 #include "msp430f427a.h"
339 000000 #elif defined (__MSP430F435__)
340 000000 #include "msp430f435.h"
342 000000 #elif defined (__MSP430F436__)
343 000000 #include "msp430f436.h"
345 000000 #elif defined (__MSP430F437__)
346 000000 #include "msp430f437.h"
348 000000 #elif defined (__MSP430F4351__)
349 000000 #include "msp430f4351.h"
351 000000 #elif defined (__MSP430F4361__)
352 000000 #include "msp430f4361.h"
354 000000 #elif defined (__MSP430F4371__)
355 000000 #include "msp430f4371.h"
357 000000 #elif defined (__MSP430F4481__)
358 000000 #include "msp430f4481.h"
360 000000 #elif defined (__MSP430F4491__)
361 000000 #include "msp430f4491.h"
363 000000 #elif defined (__MSP430F447__)
364 000000 #include "msp430f447.h"
366 000000 #elif defined (__MSP430F448__)
367 000000 #include "msp430f448.h"
369 000000 #elif defined (__MSP430F449__)
370 000000 #include "msp430f449.h"
372 000000 #elif defined (__MSP430FE423__)
373 000000 #include "msp430fe423.h"
375 000000 #elif defined (__MSP430FE425__)
376 000000 #include "msp430fe425.h"
378 000000 #elif defined (__MSP430FE427__)
379 000000 #include "msp430fe427.h"
381 000000 #elif defined (__MSP430FE423A__)
382 000000 #include "msp430fe423a.h"
384 000000 #elif defined (__MSP430FE425A__)
385 000000 #include "msp430fe425a.h"
387 000000 #elif defined (__MSP430FE427A__)
388 000000 #include "msp430fe427a.h"
390 000000 #elif defined (__MSP430FE4232__)
391 000000 #include "msp430fe4232.h"
393 000000 #elif defined (__MSP430FE4242__)
394 000000 #include "msp430fe4242.h"
396 000000 #elif defined (__MSP430FE4252__)
397 000000 #include "msp430fe4252.h"
399 000000 #elif defined (__MSP430FE4272__)
400 000000 #include "msp430fe4272.h"
402 000000 #elif defined (__MSP430F4783__)
403 000000 #include "msp430f4783.h"
405 000000 #elif defined (__MSP430F4793__)
406 000000 #include "msp430f4793.h"
408 000000 #elif defined (__MSP430F4784__)
409 000000 #include "msp430f4784.h"
411 000000 #elif defined (__MSP430F4794__)
412 000000 #include "msp430f4794.h"
414 000000 #elif defined (__MSP430F47126__)
415 000000 #include "msp430f47126.h"
417 000000 #elif defined (__MSP430F47127__)
418 000000 #include "msp430f47127.h"
420 000000 #elif defined (__MSP430F47163__)
421 000000 #include "msp430f47163.h"
423 000000 #elif defined (__MSP430F47173__)
424 000000 #include "msp430f47173.h"
426 000000 #elif defined (__MSP430F47183__)
427 000000 #include "msp430f47183.h"
429 000000 #elif defined (__MSP430F47193__)
430 000000 #include "msp430f47193.h"
432 000000 #elif defined (__MSP430F47166__)
433 000000 #include "msp430f47166.h"
435 000000 #elif defined (__MSP430F47176__)
436 000000 #include "msp430f47176.h"
438 000000 #elif defined (__MSP430F47186__)
439 000000 #include "msp430f47186.h"
441 000000 #elif defined (__MSP430F47196__)
442 000000 #include "msp430f47196.h"
444 000000 #elif defined (__MSP430F47167__)
445 000000 #include "msp430f47167.h"
447 000000 #elif defined (__MSP430F47177__)
448 000000 #include "msp430f47177.h"
450 000000 #elif defined (__MSP430F47187__)
451 000000 #include "msp430f47187.h"
453 000000 #elif defined (__MSP430F47197__)
454 000000 #include "msp430f47197.h"
456 000000 #elif defined (__MSP430F4250__)
457 000000 #include "msp430f4250.h"
459 000000 #elif defined (__MSP430F4260__)
460 000000 #include "msp430f4260.h"
462 000000 #elif defined (__MSP430F4270__)
463 000000 #include "msp430f4270.h"
465 000000 #elif defined (__MSP430FG4250__)
466 000000 #include "msp430fg4250.h"
468 000000 #elif defined (__MSP430FG4260__)
469 000000 #include "msp430fg4260.h"
471 000000 #elif defined (__MSP430FG4270__)
472 000000 #include "msp430fg4270.h"
474 000000 #elif defined (__MSP430FW423__)
475 000000 #include "msp430fw423.h"
477 000000 #elif defined (__MSP430FW425__)
478 000000 #include "msp430fw425.h"
480 000000 #elif defined (__MSP430FW427__)
481 000000 #include "msp430fw427.h"
483 000000 #elif defined (__MSP430FW428__)
484 000000 #include "msp430fw428.h"
486 000000 #elif defined (__MSP430FW429__)
487 000000 #include "msp430fw429.h"
489 000000 #elif defined (__MSP430FG437__)
490 000000 #include "msp430fg437.h"
492 000000 #elif defined (__MSP430FG438__)
493 000000 #include "msp430fg438.h"
495 000000 #elif defined (__MSP430FG439__)
496 000000 #include "msp430fg439.h"
498 000000 #elif defined (__MSP430F438__)
499 000000 #include "msp430f438.h"
501 000000 #elif defined (__MSP430F439__)
502 000000 #include "msp430f439.h"
504 000000 #elif defined (__MSP430F477__)
505 000000 #include "msp430f477.h"
507 000000 #elif defined (__MSP430F478__)
508 000000 #include "msp430f478.h"
510 000000 #elif defined (__MSP430F479__)
511 000000 #include "msp430f479.h"
513 000000 #elif defined (__MSP430FG477__)
514 000000 #include "msp430fg477.h"
516 000000 #elif defined (__MSP430FG478__)
517 000000 #include "msp430fg478.h"
519 000000 #elif defined (__MSP430FG479__)
520 000000 #include "msp430fg479.h"
522 000000 #elif defined (__MSP430F46161__)
523 000000 #include "msp430f46161.h"
525 000000 #elif defined (__MSP430F46171__)
526 000000 #include "msp430f46171.h"
528 000000 #elif defined (__MSP430F46181__)
529 000000 #include "msp430f46181.h"
531 000000 #elif defined (__MSP430F46191__)
532 000000 #include "msp430f46191.h"
534 000000 #elif defined (__MSP430F4616__)
535 000000 #include "msp430f4616.h"
537 000000 #elif defined (__MSP430F4617__)
538 000000 #include "msp430f4617.h"
540 000000 #elif defined (__MSP430F4618__)
541 000000 #include "msp430f4618.h"
543 000000 #elif defined (__MSP430F4619__)
544 000000 #include "msp430f4619.h"
546 000000 #elif defined (__MSP430FG4616__)
547 000000 #include "msp430fg4616.h"
549 000000 #elif defined (__MSP430FG4617__)
550 000000 #include "msp430fg4617.h"
552 000000 #elif defined (__MSP430FG4618__)
553 000000 #include "msp430fg4618.h"
555 000000 #elif defined (__MSP430FG4619__)
556 000000 #include "msp430fg4619.h"
558 000000 #elif defined (__MSP430F5418__)
559 000000 #include "msp430f5418.h"
561 000000 #elif defined (__MSP430F5419__)
562 000000 #include "msp430f5419.h"
564 000000 #elif defined (__MSP430F5435__)
565 000000 #include "msp430f5435.h"
567 000000 #elif defined (__MSP430F5436__)
568 000000 #include "msp430f5436.h"
570 000000 #elif defined (__MSP430F5437__)
571 000000 #include "msp430f5437.h"
573 000000 #elif defined (__MSP430F5438__)
574 000000 #include "msp430f5438.h"
576 000000 #elif defined (__XMS430F5438__)
577 000000 #include "xms430f5438.h"
579 000000 #elif defined (__MSP430F5418A__)
580 000000 #include "msp430f5418a.h"
582 000000 #elif defined (__MSP430F5419A__)
583 000000 #include "msp430f5419a.h"
585 000000 #elif defined (__MSP430F5435A__)
586 000000 #include "msp430f5435a.h"
588 000000 #elif defined (__MSP430F5436A__)
589 000000 #include "msp430f5436a.h"
591 000000 #elif defined (__MSP430F5437A__)
592 000000 #include "msp430f5437a.h"
594 000000 #elif defined (__MSP430F5438A__)
595 000000 #include "msp430f5438a.h"
597 000000 #elif defined (__MSP430F5304__)
598 000000 #include "msp430f5304.h"
600 000000 #elif defined (__MSP430F5308__)
601 000000 #include "msp430f5308.h"
603 000000 #elif defined (__MSP430F5309__)
604 000000 #include "msp430f5309.h"
606 000000 #elif defined (__MSP430F5310__)
607 000000 #include "msp430f5310.h"
609 000000 #elif defined (__MSP430F5340__)
610 000000 #include "msp430f5340.h"
612 000000 #elif defined (__MSP430F5341__)
613 000000 #include "msp430f5341.h"
615 000000 #elif defined (__MSP430F5342__)
616 000000 #include "msp430f5342.h"
618 000000 #elif defined (__MSP430F5324__)
619 000000 #include "msp430f5324.h"
621 000000 #elif defined (__MSP430F5325__)
622 000000 #include "msp430f5325.h"
624 000000 #elif defined (__MSP430F5326__)
625 000000 #include "msp430f5326.h"
627 000000 #elif defined (__MSP430F5327__)
628 000000 #include "msp430f5327.h"
630 000000 #elif defined (__MSP430F5328__)
631 000000 #include "msp430f5328.h"
633 000000 #elif defined (__MSP430F5329__)
634 000000 #include "msp430f5329.h"
636 000000 #elif defined (__MSP430F5500__)
637 000000 #include "msp430f5500.h"
639 000000 #elif defined (__MSP430F5501__)
640 000000 #include "msp430f5501.h"
642 000000 #elif defined (__MSP430F5502__)
643 000000 #include "msp430f5502.h"
645 000000 #elif defined (__MSP430F5503__)
646 000000 #include "msp430f5503.h"
648 000000 #elif defined (__MSP430F5504__)
649 000000 #include "msp430f5504.h"
651 000000 #elif defined (__MSP430F5505__)
652 000000 #include "msp430f5505.h"
654 000000 #elif defined (__MSP430F5506__)
655 000000 #include "msp430f5506.h"
657 000000 #elif defined (__MSP430F5507__)
658 000000 #include "msp430f5507.h"
660 000000 #elif defined (__MSP430F5508__)
661 000000 #include "msp430f5508.h"
663 000000 #elif defined (__MSP430F5509__)
664 000000 #include "msp430f5509.h"
666 000000 #elif defined (__MSP430F5510__)
667 000000 #include "msp430f5510.h"
669 000000 #elif defined (__MSP430F5513__)
670 000000 #include "msp430f5513.h"
672 000000 #elif defined (__MSP430F5514__)
673 000000 #include "msp430f5514.h"
675 000000 #elif defined (__MSP430F5515__)
676 000000 #include "msp430f5515.h"
678 000000 #elif defined (__MSP430F5517__)
679 000000 #include "msp430f5517.h"
681 000000 #elif defined (__MSP430F5519__)
682 000000 #include "msp430f5519.h"
684 000000 #elif defined (__MSP430F5521__)
685 000000 #include "msp430f5521.h"
687 000000 #elif defined (__MSP430F5522__)
688 000000 #include "msp430f5522.h"
690 000000 #elif defined (__MSP430F5524__)
691 000000 #include "msp430f5524.h"
693 000000 #elif defined (__MSP430F5525__)
694 000000 #include "msp430f5525.h"
696 000000 #elif defined (__MSP430F5526__)
697 000000 #include "msp430f5526.h"
699 000000 #elif defined (__MSP430F5527__)
700 000000 #include "msp430f5527.h"
702 000000 #elif defined (__MSP430F5528__)
703 000000 #include "msp430f5528.h"
705 000000 #elif defined (__MSP430F5529__)
706 000000 #include "msp430f5529.h"
708 000000 #elif defined (__MSP430P112__)
709 000000 #include "msp430p112.h"
711 000000 #elif defined (__MSP430P313__)
712 000000 #include "msp430p313.h"
714 000000 #elif defined (__MSP430P315__)
715 000000 #include "msp430p315.h"
717 000000 #elif defined (__MSP430P315S__)
718 000000 #include "msp430p315s.h"
720 000000 #elif defined (__MSP430P325__)
721 000000 #include "msp430p325.h"
723 000000 #elif defined (__MSP430P337__)
724 000000 #include "msp430p337.h"
726 000000 #elif defined (__CC430F5133__)
727 000000 #include "cc430f5133.h"
729 000000 #elif defined (__CC430F5135__)
730 000000 #include "cc430f5135.h"
732 000000 #elif defined (__CC430F5137__)
733 000000 #include "cc430f5137.h"
735 000000 #elif defined (__CC430F6125__)
736 000000 #include "cc430f6125.h"
738 000000 #elif defined (__CC430F6126__)
739 000000 #include "cc430f6126.h"
741 000000 #elif defined (__CC430F6127__)
742 000000 #include "cc430f6127.h"
744 000000 #elif defined (__CC430F6135__)
745 000000 #include "cc430f6135.h"
747 000000 #elif defined (__CC430F6137__)
748 000000 #include "cc430f6137.h"
750 000000 #elif defined (__MSP430F5630__)
751 000000 #include "msp430f5630.h"
753 000000 #elif defined (__MSP430F5631__)
754 000000 #include "msp430f5631.h"
756 000000 #elif defined (__MSP430F5632__)
757 000000 #include "msp430f5632.h"
759 000000 #elif defined (__MSP430F5633__)
760 000000 #include "msp430f5633.h"
762 000000 #elif defined (__MSP430F5634__)
763 000000 #include "msp430f5634.h"
765 000000 #elif defined (__MSP430F5635__)
766 000000 #include "msp430f5635.h"
768 000000 #elif defined (__MSP430F5636__)
769 000000 #include "msp430f5636.h"
771 000000 #elif defined (__MSP430F5637__)
772 000000 #include "msp430f5637.h"
774 000000 #elif defined (__MSP430F5638__)
775 000000 #include "msp430f5638.h"
777 000000 #elif defined (__MSP430F6630__)
778 000000 #include "msp430f6630.h"
780 000000 #elif defined (__MSP430F6631__)
781 000000 #include "msp430f6631.h"
783 000000 #elif defined (__MSP430F6632__)
784 000000 #include "msp430f6632.h"
786 000000 #elif defined (__MSP430F6633__)
787 000000 #include "msp430f6633.h"
789 000000 #elif defined (__MSP430F6634__)
790 000000 #include "msp430f6634.h"
792 000000 #elif defined (__MSP430F6635__)
793 000000 #include "msp430f6635.h"
795 000000 #elif defined (__MSP430F6636__)
796 000000 #include "msp430f6636.h"
798 000000 #elif defined (__MSP430F6637__)
799 000000 #include "msp430f6637.h"
801 000000 #elif defined (__MSP430F6638__)
802 000000 #include "msp430f6638.h"
804 000000 #elif defined (__MSP430L092__)
805 000000 #include "msp430l092.h"
807 000000 #elif defined (__MSP430C091__)
808 000000 #include "msp430c091.h"
810 000000 #elif defined (__MSP430C092__)
811 000000 #include "msp430c092.h"
813 000000 #elif defined (__MSP430F5131__)
814 000000 #include "msp430f5131.h"
816 000000 #elif defined (__MSP430F5151__)
817 000000 #include "msp430f5151.h"
819 000000 #elif defined (__MSP430F5171__)
820 000000 #include "msp430f5171.h"
822 000000 #elif defined (__MSP430F5132__)
823 000000 #include "msp430f5132.h"
825 000000 #elif defined (__MSP430F5152__)
826 000000 #include "msp430f5152.h"
828 000000 #elif defined (__MSP430F5172__)
829 000000 #include "msp430f5172.h"
831 000000 #elif defined (__MSP430FR5720__)
832 000000 #include "msp430fr5720.h"
834 000000 #elif defined (__MSP430FR5725__)
835 000000 #include "msp430fr5725.h"
837 000000 #elif defined (__MSP430FR5728__)
838 000000 #include "msp430fr5728.h"
840 000000 #elif defined (__MSP430FR5729__)
841 000000 #include "msp430fr5729.h"
843 000000 #elif defined (__MSP430FR5730__)
844 000000 #include "msp430fr5730.h"
846 000000 #elif defined (__MSP430FR5735__)
847 000000 #include "msp430fr5735.h"
849 000000 #elif defined (__MSP430FR5738__)
850 000000 #include "msp430fr5738.h"
852 000000 #elif defined (__MSP430FR5739__)
853 000000 #include "msp430fr5739.h"
855 000000 #elif defined (__MSP430G2211__)
856 000000 #include "msp430g2211.h"
858 000000 #elif defined (__MSP430G2201__)
859 000000 #include "msp430g2201.h"
861 000000 #elif defined (__MSP430G2111__)
862 000000 #include "msp430g2111.h"
864 000000 #elif defined (__MSP430G2101__)
865 000000 #include "msp430g2101.h"
867 000000 #elif defined (__MSP430G2001__)
868 000000 #include "msp430g2001.h"
870 000000 #elif defined (__MSP430G2231__)
871 000000 #include "msp430g2231.h"
873 000000 #elif defined (__MSP430G2221__)
874 000000 #include "msp430g2221.h"
876 000000 #elif defined (__MSP430G2131__)
877 000000 #include "msp430g2131.h"
879 000000 #elif defined (__MSP430G2121__)
880 000000 #include "msp430g2121.h"
882 000000 #elif defined (__MSP430AFE221__)
883 000000 #include "msp430afe221.h"
885 000000 #elif defined (__MSP430AFE231__)
886 000000 #include "msp430afe231.h"
888 000000 #elif defined (__MSP430AFE251__)
889 000000 #include "msp430afe251.h"
891 000000 #elif defined (__MSP430AFE222__)
892 000000 #include "msp430afe222.h"
894 000000 #elif defined (__MSP430AFE232__)
895 000000 #include "msp430afe232.h"
897 000000 #elif defined (__MSP430AFE252__)
898 000000 #include "msp430afe252.h"
900 000000 #elif defined (__MSP430AFE223__)
901 000000 #include "msp430afe223.h"
903 000000 #elif defined (__MSP430AFE233__)
904 000000 #include "msp430afe233.h"
906 000000 #elif defined (__MSP430AFE253__)
907 000000 #include "msp430afe253.h"
909 000000 #elif defined (__MSP430G2102__)
910 000000 #include "msp430g2102.h"
912 000000 #elif defined (__MSP430G2202__)
913 000000 #include "msp430g2202.h"
915 000000 #elif defined (__MSP430G2302__)
916 000000 #include "msp430g2302.h"
918 000000 #elif defined (__MSP430G2402__)
919 000000 #include "msp430g2402.h"
921 000000 #elif defined (__MSP430G2132__)
922 000000 #include "msp430g2132.h"
924 000000 #elif defined (__MSP430G2232__)
925 000000 #include "msp430g2232.h"
927 000000 #elif defined (__MSP430G2332__)
928 000000 #include "msp430g2332.h"
930 000000 #elif defined (__MSP430G2432__)
931 000000 #include "msp430g2432.h"
933 000000 #elif defined (__MSP430G2112__)
934 000000 #include "msp430g2112.h"
936 000000 #elif defined (__MSP430G2212__)
937 000000 #include "msp430g2212.h"
939 000000 #elif defined (__MSP430G2312__)
940 000000 #include "msp430g2312.h"
942 000000 #elif defined (__MSP430G2412__)
943 000000 #include "msp430g2412.h"
945 000000 #elif defined (__MSP430G2152__)
946 000000 #include "msp430g2152.h"
948 000000 #elif defined (__MSP430G2252__)
949 000000 #include "msp430g2252.h"
951 000000 #elif defined (__MSP430G2352__)
952 000000 #include "msp430g2352.h"
954 000000 #elif defined (__MSP430G2452__)
955 000000 #include "msp430g2452.h"
957 000000 #elif defined (__MSP430G2113__)
958 000000 #include "msp430g2113.h"
960 000000 #elif defined (__MSP430G2213__)
961 000000 #include "msp430g2213.h"
963 000000 #elif defined (__MSP430G2313__)
964 000000 #include "msp430g2313.h"
966 000000 #elif defined (__MSP430G2413__)
967 000000 #include "msp430g2413.h"
969 000000 #elif defined (__MSP430G2513__)
970 000000 #include "msp430g2513.h"
972 000000 #elif defined (__MSP430G2153__)
973 000000 #include "msp430g2153.h"
975 000000 #elif defined (__MSP430G2253__)
976 000000 #include "msp430g2253.h"
978 000000 #elif defined (__MSP430G2353__)
979 000000 #include "msp430g2353.h"
981 000000 #elif defined (__MSP430G2453__)
982 000000 #include "msp430g2453.h"
984 000000 #elif defined (__MSP430G2553__)
985 000000 #include "msp430g2553.h"
1 000000 /***********************************************
*********************
2 000000 *
3 000000 * Standard register and bit definitions for the
Texas Instruments
4 000000 * MSP430 microcontroller.
5 000000 *
6 000000 * This file supports assembler and C development
for
7 000000 * MSP430G2553 devices.
8 000000 *
9 000000 * Texas Instruments, Version 1.0
10 000000 *
11 000000 * Rev. 1.0, Setup
12 000000 *
13 000000 ************************************************
********************/
14 000000
15 000000 #ifndef __MSP430G2553
16 000000 #define __MSP430G2553
17 000000
18 000000 #ifdef __IAR_SYSTEMS_ICC__
19 000000 #ifndef _SYSTEM_BUILD
20 000000 #pragma system_include
21 000000 #endif
22 000000 #endif
23 000000
24 000000 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /*
0x2b = 43 dec */
25 000000 #error msp430g2553.h file for use with
ICC430/A430 only
26 000000 #endif
27 000000
28 000000
29 000000 #ifdef __IAR_SYSTEMS_ICC__
30 000000 #include "in430.h"
31 000000 #pragma language=extended
33 000000 #define DEFC(name, address) __no_init volatile
unsigned char name @ address;
34 000000 #define DEFW(name, address) __no_init volatile
unsigned short name @ address;
35 000000 #define DEFXC volatile unsigned char
36 000000 #define DEFXW volatile unsigned short
38 000000 #endif /* __IAR_SYSTEMS_ICC__ */
39 000000
40 000000
41 000000 #ifdef __IAR_SYSTEMS_ASM__
42 000000 #define DEFC(name, address) sfrb name =
address;
43 000000 #define DEFW(name, address) sfrw name =
address;
44 000000
45 000000 #endif /* __IAR_SYSTEMS_ASM__*/
46 000000
47 000000 #ifdef __cplusplus
48 000000 #define READ_ONLY
49 000000 #else
50 000000 #define READ_ONLY const
51 000000 #endif
52 000000
53 000000 /***********************************************
*************
54 000000 * STANDARD BITS
55 000000 ************************************************
************/
56 000000
57 000000 #define BIT0 (0x0001u)
58 000000 #define BIT1 (0x0002u)
59 000000 #define BIT2 (0x0004u)
60 000000 #define BIT3 (0x0008u)
61 000000 #define BIT4 (0x0010u)
62 000000 #define BIT5 (0x0020u)
63 000000 #define BIT6 (0x0040u)
64 000000 #define BIT7 (0x0080u)
65 000000 #define BIT8 (0x0100u)
66 000000 #define BIT9 (0x0200u)
67 000000 #define BITA (0x0400u)
68 000000 #define BITB (0x0800u)
69 000000 #define BITC (0x1000u)
70 000000 #define BITD (0x2000u)
71 000000 #define BITE (0x4000u)
72 000000 #define BITF (0x8000u)
73 000000
74 000000 /***********************************************
*************
75 000000 * STATUS REGISTER BITS
76 000000 ************************************************
************/
77 000000
78 000000 #define C (0x0001u)
79 000000 #define Z (0x0002u)
80 000000 #define N (0x0004u)
81 000000 #define V (0x0100u)
82 000000 #define GIE (0x0008u)
83 000000 #define CPUOFF (0x0010u)
84 000000 #define OSCOFF (0x0020u)
85 000000 #define SCG0 (0x0040u)
86 000000 #define SCG1 (0x0080u)
87 000000
88 000000 /* Low Power Modes coded with Bits 4-7 in SR
*/
89 000000
90 000000 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines
for assembler */
91 000000 #define LPM0 (CPUOFF)
92 000000 #define LPM1 (SCG0+CPUOFF)
93 000000 #define LPM2 (SCG1+CPUOFF)
94 000000 #define LPM3 (SCG1+SCG0+CPUOFF)
95 000000 #define LPM4 (SCG1+SCG0+OSCOFF+CP
UOFF)
96 000000 /* End #defines for assembler */
97 000000
98 000000 #else /* Begin #defines for C */
99 000000 #define LPM0_bits (CPUOFF)
100 000000 #define LPM1_bits (SCG0+CPUOFF)
101 000000 #define LPM2_bits (SCG1+CPUOFF)
102 000000 #define LPM3_bits (SCG1+SCG0+CPUOFF)
103 000000 #define LPM4_bits (SCG1+SCG0+OSCOFF+CP
UOFF)
105 000000 #include "in430.h"
107 000000 #define LPM0 _BIS_SR(LPM0_bits) /*
Enter Low Power Mode 0 */
108 000000 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit
Low Power Mode 0 */
109 000000 #define LPM1 _BIS_SR(LPM1_bits) /*
Enter Low Power Mode 1 */
110 000000 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit
Low Power Mode 1 */
111 000000 #define LPM2 _BIS_SR(LPM2_bits) /*
Enter Low Power Mode 2 */
112 000000 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit
Low Power Mode 2 */
113 000000 #define LPM3 _BIS_SR(LPM3_bits) /*
Enter Low Power Mode 3 */
114 000000 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit
Low Power Mode 3 */
115 000000 #define LPM4 _BIS_SR(LPM4_bits) /*
Enter Low Power Mode 4 */
116 000000 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit
Low Power Mode 4 */
117 000000 #endif /* End #defines for C */
118 000000
119 000000 /***********************************************
*************
120 000000 * PERIPHERAL FILE MAP
121 000000 ************************************************
************/
122 000000
123 000000 /***********************************************
*************
124 000000 * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL
BITS
125 000000 ************************************************
************/
126 000000
127 000000 #define IE1_ (0x0000u) /*
Interrupt Enable 1 */
128 000000 DEFC( IE1 , IE1_)
129 000000 #define WDTIE (0x01) /*
Watchdog Interrupt Enable */
130 000000 #define OFIE (0x02) /* Osc.
Fault Interrupt Enable */
131 000000 #define NMIIE (0x10) /* NMI
Interrupt Enable */
132 000000 #define ACCVIE (0x20) /* Flash
Access Violation Interrupt Enable */
133 000000
134 000000 #define IFG1_ (0x0002u) /*
Interrupt Flag 1 */
135 000000 DEFC( IFG1 , IFG1_)
136 000000 #define WDTIFG (0x01) /*
Watchdog Interrupt Flag */
137 000000 #define OFIFG (0x02) /* Osc.
Fault Interrupt Flag */
138 000000 #define PORIFG (0x04) /* Power
On Interrupt Flag */
139 000000 #define RSTIFG (0x08) /* Reset
Interrupt Flag */
140 000000 #define NMIIFG (0x10) /* NMI
Interrupt Flag */
141 000000
142 000000 #define IE2_ (0x0001u) /*
Interrupt Enable 2 */
143 000000 DEFC( IE2 , IE2_)
144 000000 #define UC0IE IE2
145 000000 #define UCA0RXIE (0x01)
146 000000 #define UCA0TXIE (0x02)
147 000000 #define UCB0RXIE (0x04)
148 000000 #define UCB0TXIE (0x08)
149 000000
150 000000 #define IFG2_ (0x0003u) /*
Interrupt Flag 2 */
151 000000 DEFC( IFG2 , IFG2_)
152 000000 #define UC0IFG IFG2
153 000000 #define UCA0RXIFG (0x01)
154 000000 #define UCA0TXIFG (0x02)
155 000000 #define UCB0RXIFG (0x04)
156 000000 #define UCB0TXIFG (0x08)
157 000000
158 000000 /***********************************************
*************
159 000000 * ADC10
160 000000 ************************************************
************/
161 000000 #define __MSP430_HAS_ADC10__ /*
Definition to show that Module is available
*/
162 000000
163 000000 #define ADC10DTC0_ (0x0048u) /*
ADC10 Data Transfer Control 0 */
164 000000 DEFC( ADC10DTC0 , ADC10DTC0_)
165 000000 #define ADC10DTC1_ (0x0049u) /*
ADC10 Data Transfer Control 1 */
166 000000 DEFC( ADC10DTC1 , ADC10DTC1_)
167 000000 #define ADC10AE0_ (0x004Au) /*
ADC10 Analog Enable 0 */
168 000000 DEFC( ADC10AE0 , ADC10AE0_)
169 000000
170 000000 #define ADC10CTL0_ (0x01B0u) /*
ADC10 Control 0 */
171 000000 DEFW( ADC10CTL0 , ADC10CTL0_)
172 000000 #define ADC10CTL1_ (0x01B2u) /*
ADC10 Control 1 */
173 000000 DEFW( ADC10CTL1 , ADC10CTL1_)
174 000000 #define ADC10MEM_ (0x01B4u) /*
ADC10 Memory */
175 000000 DEFW( ADC10MEM , ADC10MEM_)
176 000000 #define ADC10SA_ (0x01BCu) /*
ADC10 Data Transfer Start Address */
177 000000 DEFW( ADC10SA , ADC10SA_)
178 000000
179 000000 /* ADC10CTL0 */
180 000000 #define ADC10SC (0x001) /* ADC10
Start Conversion */
181 000000 #define ENC (0x002) /* ADC10
Enable Conversion */
182 000000 #define ADC10IFG (0x004) /* ADC10
Interrupt Flag */
183 000000 #define ADC10IE (0x008) /* ADC10
Interrupt Enalbe */
184 000000 #define ADC10ON (0x010) /* ADC10
On/Enable */
185 000000 #define REFON (0x020) /* ADC10
Reference on */
186 000000 #define REF2_5V (0x040) /* ADC10
Ref 0:1.5V / 1:2.5V */
187 000000 #define MSC (0x080) /* ADC10
Multiple SampleConversion */
188 000000 #define REFBURST (0x100) /* ADC10
Reference Burst Mode */
189 000000 #define REFOUT (0x200) /* ADC10
Enalbe output of Ref. */
190 000000 #define ADC10SR (0x400) /* ADC10
Sampling Rate 0:200ksps / 1:50ksps */
191 000000 #define ADC10SHT0 (0x800) /* ADC10
Sample Hold Select Bit: 0 */
192 000000 #define ADC10SHT1 (0x1000u) /*
ADC10 Sample Hold Select Bit: 1 */
193 000000 #define SREF0 (0x2000u) /*
ADC10 Reference Select Bit: 0 */
194 000000 #define SREF1 (0x4000u) /*
ADC10 Reference Select Bit: 1 */
195 000000 #define SREF2 (0x8000u) /*
ADC10 Reference Select Bit: 2 */
196 000000 #define ADC10SHT_0 (0*0x800u) /* 4 x
ADC10CLKs */
197 000000 #define ADC10SHT_1 (1*0x800u) /* 8 x
ADC10CLKs */
198 000000 #define ADC10SHT_2 (2*0x800u) /* 16 x
ADC10CLKs */
199 000000 #define ADC10SHT_3 (3*0x800u) /* 64 x
ADC10CLKs */
200 000000
201 000000 #define SREF_0 (0*0x2000u) /* VR+
= AVCC and VR- = AVSS */
202 000000 #define SREF_1 (1*0x2000u) /* VR+
= VREF+ and VR- = AVSS */
203 000000 #define SREF_2 (2*0x2000u) /* VR+
= VEREF+ and VR- = AVSS */
204 000000 #define SREF_3 (3*0x2000u) /* VR+
= VEREF+ and VR- = AVSS */
205 000000 #define SREF_4 (4*0x2000u) /* VR+
= AVCC and VR- = VREF-/VEREF- */
206 000000 #define SREF_5 (5*0x2000u) /* VR+
= VREF+ and VR- = VREF-/VEREF- */
207 000000 #define SREF_6 (6*0x2000u) /* VR+
= VEREF+ and VR- = VREF-/VEREF- */
208 000000 #define SREF_7 (7*0x2000u) /* VR+
= VEREF+ and VR- = VREF-/VEREF- */
209 000000
210 000000 /* ADC10CTL1 */
211 000000 #define ADC10BUSY (0x0001u) /*
ADC10 BUSY */
212 000000 #define CONSEQ0 (0x0002u) /*
ADC10 Conversion Sequence Select 0 */
213 000000 #define CONSEQ1 (0x0004u) /*
ADC10 Conversion Sequence Select 1 */
214 000000 #define ADC10SSEL0 (0x0008u) /*
ADC10 Clock Source Select Bit: 0 */
215 000000 #define ADC10SSEL1 (0x0010u) /*
ADC10 Clock Source Select Bit: 1 */
216 000000 #define ADC10DIV0 (0x0020u) /*
ADC10 Clock Divider Select Bit: 0 */
217 000000 #define ADC10DIV1 (0x0040u) /*
ADC10 Clock Divider Select Bit: 1 */
218 000000 #define ADC10DIV2 (0x0080u) /*
ADC10 Clock Divider Select Bit: 2 */
219 000000 #define ISSH (0x0100u) /*
ADC10 Invert Sample Hold Signal */
220 000000 #define ADC10DF (0x0200u) /*
ADC10 Data Format 0:binary 1:2's complement
*/
221 000000 #define SHS0 (0x0400u) /*
ADC10 Sample/Hold Source Bit: 0 */
222 000000 #define SHS1 (0x0800u) /*
ADC10 Sample/Hold Source Bit: 1 */
223 000000 #define INCH0 (0x1000u) /*
ADC10 Input Channel Select Bit: 0 */
224 000000 #define INCH1 (0x2000u) /*
ADC10 Input Channel Select Bit: 1 */
225 000000 #define INCH2 (0x4000u) /*
ADC10 Input Channel Select Bit: 2 */
226 000000 #define INCH3 (0x8000u) /*
ADC10 Input Channel Select Bit: 3 */
227 000000
228 000000 #define CONSEQ_0 (0*2u) /*
Single channel single conversion */
229 000000 #define CONSEQ_1 (1*2u) /*
Sequence of channels */
230 000000 #define CONSEQ_2 (2*2u) /*
Repeat single channel */
231 000000 #define CONSEQ_3 (3*2u) /*
Repeat sequence of channels */
232 000000
233 000000 #define ADC10SSEL_0 (0*8u) /*
ADC10OSC */
234 000000 #define ADC10SSEL_1 (1*8u) /* ACLK
*/
235 000000 #define ADC10SSEL_2 (2*8u) /* MCLK
*/
236 000000 #define ADC10SSEL_3 (3*8u) /*
SMCLK */
237 000000
238 000000 #define ADC10DIV_0 (0*0x20u) /*
ADC10 Clock Divider Select 0 */
239 000000 #define ADC10DIV_1 (1*0x20u) /*
ADC10 Clock Divider Select 1 */
240 000000 #define ADC10DIV_2 (2*0x20u) /*
ADC10 Clock Divider Select 2 */
241 000000 #define ADC10DIV_3 (3*0x20u) /*
ADC10 Clock Divider Select 3 */
242 000000 #define ADC10DIV_4 (4*0x20u) /*
ADC10 Clock Divider Select 4 */
243 000000 #define ADC10DIV_5 (5*0x20u) /*
ADC10 Clock Divider Select 5 */
244 000000 #define ADC10DIV_6 (6*0x20u) /*
ADC10 Clock Divider Select 6 */
245 000000 #define ADC10DIV_7 (7*0x20u) /*
ADC10 Clock Divider Select 7 */
246 000000
247 000000 #define SHS_0 (0*0x400u) /*
ADC10SC */
248 000000 #define SHS_1 (1*0x400u) /* TA3
OUT1 */
249 000000 #define SHS_2 (2*0x400u) /* TA3
OUT0 */
250 000000 #define SHS_3 (3*0x400u) /* TA3
OUT2 */
251 000000
252 000000 #define INCH_0 (0*0x1000u) /*
Selects Channel 0 */
253 000000 #define INCH_1 (1*0x1000u) /*
Selects Channel 1 */
254 000000 #define INCH_2 (2*0x1000u) /*
Selects Channel 2 */
255 000000 #define INCH_3 (3*0x1000u) /*
Selects Channel 3 */
256 000000 #define INCH_4 (4*0x1000u) /*
Selects Channel 4 */
257 000000 #define INCH_5 (5*0x1000u) /*
Selects Channel 5 */
258 000000 #define INCH_6 (6*0x1000u) /*
Selects Channel 6 */
259 000000 #define INCH_7 (7*0x1000u) /*
Selects Channel 7 */
260 000000 #define INCH_8 (8*0x1000u) /*
Selects Channel 8 */
261 000000 #define INCH_9 (9*0x1000u) /*
Selects Channel 9 */
262 000000 #define INCH_10 (10*0x1000u) /*
Selects Channel 10 */
263 000000 #define INCH_11 (11*0x1000u) /*
Selects Channel 11 */
264 000000 #define INCH_12 (12*0x1000u) /*
Selects Channel 12 */
265 000000 #define INCH_13 (13*0x1000u) /*
Selects Channel 13 */
266 000000 #define INCH_14 (14*0x1000u) /*
Selects Channel 14 */
267 000000 #define INCH_15 (15*0x1000u) /*
Selects Channel 15 */
268 000000
269 000000 /* ADC10DTC0 */
270 000000 #define ADC10FETCH (0x001) /* This
bit should normally be reset */
271 000000 #define ADC10B1 (0x002) /* ADC10
block one */
272 000000 #define ADC10CT (0x004) /* ADC10
continuous transfer */
273 000000 #define ADC10TB (0x008) /* ADC10
two-block mode */
274 000000 #define ADC10DISABLE (0x000) /*
ADC10DTC1 */
275 000000
276 000000 /***********************************************
*************
277 000000 * Basic Clock Module
278 000000 ************************************************
************/
279 000000 #define __MSP430_HAS_BC2__ /*
Definition to show that Module is available
*/
280 000000
281 000000 #define DCOCTL_ (0x0056u) /* DCO
Clock Frequency Control */
282 000000 DEFC( DCOCTL , DCOCTL_)
283 000000 #define BCSCTL1_ (0x0057u) /* Basic
Clock System Control 1 */
284 000000 DEFC( BCSCTL1 , BCSCTL1_)
285 000000 #define BCSCTL2_ (0x0058u) /* Basic
Clock System Control 2 */
286 000000 DEFC( BCSCTL2 , BCSCTL2_)
287 000000 #define BCSCTL3_ (0x0053u) /* Basic
Clock System Control 3 */
288 000000 DEFC( BCSCTL3 , BCSCTL3_)
289 000000
290 000000 #define MOD0 (0x01) /*
Modulation Bit 0 */
291 000000 #define MOD1 (0x02) /*
Modulation Bit 1 */
292 000000 #define MOD2 (0x04) /*
Modulation Bit 2 */
293 000000 #define MOD3 (0x08) /*
Modulation Bit 3 */
294 000000 #define MOD4 (0x10) /*
Modulation Bit 4 */
295 000000 #define DCO0 (0x20) /* DCO
Select Bit 0 */
296 000000 #define DCO1 (0x40) /* DCO
Select Bit 1 */
297 000000 #define DCO2 (0x80) /* DCO
Select Bit 2 */
298 000000
299 000000 #define RSEL0 (0x01) /* Range
Select Bit 0 */
300 000000 #define RSEL1 (0x02) /* Range
Select Bit 1 */
301 000000 #define RSEL2 (0x04) /* Range
Select Bit 2 */
302 000000 #define RSEL3 (0x08) /* Range
Select Bit 3 */
303 000000 #define DIVA0 (0x10) /* ACLK
Divider 0 */
304 000000 #define DIVA1 (0x20) /* ACLK
Divider 1 */
305 000000 #define XTS (0x40) /* LFXTCLK
0:Low Freq. / 1: High Freq. */
306 000000 #define XT2OFF (0x80) /* Enable
XT2CLK */
307 000000
308 000000 #define DIVA_0 (0x00) /* ACLK
Divider 0: /1 */
309 000000 #define DIVA_1 (0x10) /* ACLK
Divider 1: /2 */
310 000000 #define DIVA_2 (0x20) /* ACLK
Divider 2: /4 */
311 000000 #define DIVA_3 (0x30) /* ACLK
Divider 3: /8 */
312 000000
313 000000 #define DIVS0 (0x02) /* SMCLK
Divider 0 */
314 000000 #define DIVS1 (0x04) /* SMCLK
Divider 1 */
315 000000 #define SELS (0x08) /* SMCLK
Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK
*/
316 000000 #define DIVM0 (0x10) /* MCLK
Divider 0 */
317 000000 #define DIVM1 (0x20) /* MCLK
Divider 1 */
318 000000 #define SELM0 (0x40) /* MCLK
Source Select 0 */
319 000000 #define SELM1 (0x80) /* MCLK
Source Select 1 */
320 000000
321 000000 #define DIVS_0 (0x00) /* SMCLK
Divider 0: /1 */
322 000000 #define DIVS_1 (0x02) /* SMCLK
Divider 1: /2 */
323 000000 #define DIVS_2 (0x04) /* SMCLK
Divider 2: /4 */
324 000000 #define DIVS_3 (0x06) /* SMCLK
Divider 3: /8 */
325 000000
326 000000 #define DIVM_0 (0x00) /* MCLK
Divider 0: /1 */
327 000000 #define DIVM_1 (0x10) /* MCLK
Divider 1: /2 */
328 000000 #define DIVM_2 (0x20) /* MCLK
Divider 2: /4 */
329 000000 #define DIVM_3 (0x30) /* MCLK
Divider 3: /8 */
330 000000
331 000000 #define SELM_0 (0x00) /* MCLK
Source Select 0: DCOCLK */
332 000000 #define SELM_1 (0x40) /* MCLK
Source Select 1: DCOCLK */
333 000000 #define SELM_2 (0x80) /* MCLK
Source Select 2: XT2CLK/LFXTCLK */
334 000000 #define SELM_3 (0xC0) /* MCLK
Source Select 3: LFXTCLK */
335 000000
336 000000 #define LFXT1OF (0x01) /* Low/high
Frequency Oscillator Fault Flag */
337 000000 #define XT2OF (0x02) /* High
frequency oscillator 2 fault flag */
338 000000 #define XCAP0 (0x04) /* XIN/XOUT
Cap 0 */
339 000000 #define XCAP1 (0x08) /* XIN/XOUT
Cap 1 */
340 000000 #define LFXT1S0 (0x10) /* Mode 0
for LFXT1 (XTS = 0) */
341 000000 #define LFXT1S1 (0x20) /* Mode 1
for LFXT1 (XTS = 0) */
342 000000 #define XT2S0 (0x40) /* Mode 0
for XT2 */
343 000000 #define XT2S1 (0x80) /* Mode 1
for XT2 */
344 000000
345 000000 #define XCAP_0 (0x00) /* XIN/XOUT
Cap : 0 pF */
346 000000 #define XCAP_1 (0x04) /* XIN/XOUT
Cap : 6 pF */
347 000000 #define XCAP_2 (0x08) /* XIN/XOUT
Cap : 10 pF */
348 000000 #define XCAP_3 (0x0C) /* XIN/XOUT
Cap : 12.5 pF */
349 000000
350 000000 #define LFXT1S_0 (0x00) /* Mode 0
for LFXT1 : Normal operation */
351 000000 #define LFXT1S_1 (0x10) /* Mode 1
for LFXT1 : Reserved */
352 000000 #define LFXT1S_2 (0x20) /* Mode 2
for LFXT1 : VLO */
353 000000 #define LFXT1S_3 (0x30) /* Mode 3
for LFXT1 : Digital input signal */
354 000000
355 000000 #define XT2S_0 (0x00) /* Mode 0
for XT2 : 0.4 - 1 MHz */
356 000000 #define XT2S_1 (0x40) /* Mode 1
for XT2 : 1 - 4 MHz */
357 000000 #define XT2S_2 (0x80) /* Mode 2
for XT2 : 2 - 16 MHz */
358 000000 #define XT2S_3 (0xC0) /* Mode 3
for XT2 : Digital input signal */
359 000000
360 000000 /***********************************************
*************
361 000000 * Comparator A
362 000000 ************************************************
************/
363 000000 #define __MSP430_HAS_CAPLUS__ /*
Definition to show that Module is available
*/
364 000000
365 000000 #define CACTL1_ (0x0059u) /*
Comparator A Control 1 */
366 000000 DEFC( CACTL1 , CACTL1_)
367 000000 #define CACTL2_ (0x005Au) /*
Comparator A Control 2 */
368 000000 DEFC( CACTL2 , CACTL2_)
369 000000 #define CAPD_ (0x005Bu) /*
Comparator A Port Disable */
370 000000 DEFC( CAPD , CAPD_)
371 000000
372 000000 #define CAIFG (0x01) /* Comp. A
Interrupt Flag */
373 000000 #define CAIE (0x02) /* Comp. A
Interrupt Enable */
374 000000 #define CAIES (0x04) /* Comp. A
Int. Edge Select: 0:rising / 1:falling
*/
375 000000 #define CAON (0x08) /* Comp. A
enable */
376 000000 #define CAREF0 (0x10) /* Comp. A
Internal Reference Select 0 */
377 000000 #define CAREF1 (0x20) /* Comp. A
Internal Reference Select 1 */
378 000000 #define CARSEL (0x40) /* Comp. A
Internal Reference Enable */
379 000000 #define CAEX (0x80) /* Comp. A
Exchange Inputs */
380 000000
381 000000 #define CAREF_0 (0x00) /* Comp. A
Int. Ref. Select 0 : Off */
382 000000 #define CAREF_1 (0x10) /* Comp. A
Int. Ref. Select 1 : 0.25*Vcc */
383 000000 #define CAREF_2 (0x20) /* Comp. A
Int. Ref. Select 2 : 0.5*Vcc */
384 000000 #define CAREF_3 (0x30) /* Comp. A
Int. Ref. Select 3 : Vt*/
385 000000
386 000000 #define CAOUT (0x01) /* Comp. A
Output */
387 000000 #define CAF (0x02) /* Comp. A
Enable Output Filter */
388 000000 #define P2CA0 (0x04) /* Comp. A
+Terminal Multiplexer */
389 000000 #define P2CA1 (0x08) /* Comp. A
-Terminal Multiplexer */
390 000000 #define P2CA2 (0x10) /* Comp. A
-Terminal Multiplexer */
391 000000 #define P2CA3 (0x20) /* Comp. A
-Terminal Multiplexer */
392 000000 #define P2CA4 (0x40) /* Comp. A
+Terminal Multiplexer */
393 000000 #define CASHORT (0x80) /* Comp. A
Short + and - Terminals */
394 000000
395 000000 #define CAPD0 (0x01) /* Comp. A
Disable Input Buffer of Port Register .0
*/
396 000000 #define CAPD1 (0x02) /* Comp. A
Disable Input Buffer of Port Register .1
*/
397 000000 #define CAPD2 (0x04) /* Comp. A
Disable Input Buffer of Port Register .2
*/
398 000000 #define CAPD3 (0x08) /* Comp. A
Disable Input Buffer of Port Register .3
*/
399 000000 #define CAPD4 (0x10) /* Comp. A
Disable Input Buffer of Port Register .4
*/
400 000000 #define CAPD5 (0x20) /* Comp. A
Disable Input Buffer of Port Register .5
*/
401 000000 #define CAPD6 (0x40) /* Comp. A
Disable Input Buffer of Port Register .6
*/
402 000000 #define CAPD7 (0x80) /* Comp. A
Disable Input Buffer of Port Register .7
*/
403 000000
404 000000 /***********************************************
**************
405 000000 * Flash Memory
406 000000 ************************************************
*************/
407 000000 #define __MSP430_HAS_FLASH2__ /*
Definition to show that Module is available
*/
408 000000
409 000000 #define FCTL1_ (0x0128u) /* FLASH
Control 1 */
410 000000 DEFW( FCTL1 , FCTL1_)
411 000000 #define FCTL2_ (0x012Au) /* FLASH
Control 2 */
412 000000 DEFW( FCTL2 , FCTL2_)
413 000000 #define FCTL3_ (0x012Cu) /* FLASH
Control 3 */
414 000000 DEFW( FCTL3 , FCTL3_)
415 000000
416 000000 #define FRKEY (0x9600u) /* Flash
key returned by read */
417 000000 #define FWKEY (0xA500u) /* Flash
key for write */
418 000000 #define FXKEY (0x3300u) /* for
use with XOR instruction */
419 000000
420 000000 #define ERASE (0x0002u) /* Enable
bit for Flash segment erase */
421 000000 #define MERAS (0x0004u) /* Enable
bit for Flash mass erase */
422 000000 #define WRT (0x0040u) /* Enable
bit for Flash write */
423 000000 #define BLKWRT (0x0080u) /* Enable
bit for Flash segment write */
424 000000 #define SEGWRT (0x0080u) /* old
definition */ /* Enable bit for Flash segment
write */
425 000000
426 000000 #define FN0 (0x0001u) /* Divide
Flash clock by 1 to 64 using FN0 to FN5
according to: */
427 000000 #define FN1 (0x0002u) /*
32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 +
1 */
428 000000 #ifndef FN2
429 000000 #define FN2 (0x0004u)
430 000000 #endif
431 000000 #ifndef FN3
432 000000 #define FN3 (0x0008u)
433 000000 #endif
434 000000 #ifndef FN4
435 000000 #define FN4 (0x0010u)
436 000000 #endif
437 000000 #define FN5 (0x0020u)
438 000000 #define FSSEL0 (0x0040u) /* Flash
clock select 0 */ /* to distinguish from
USART SSELx */
439 000000 #define FSSEL1 (0x0080u) /* Flash
clock select 1 */
440 000000
441 000000 #define FSSEL_0 (0x0000u) /* Flash
clock select: 0 - ACLK */
442 000000 #define FSSEL_1 (0x0040u) /* Flash
clock select: 1 - MCLK */
443 000000 #define FSSEL_2 (0x0080u) /* Flash
clock select: 2 - SMCLK */
444 000000 #define FSSEL_3 (0x00C0u) /* Flash
clock select: 3 - SMCLK */
445 000000
446 000000 #define BUSY (0x0001u) /* Flash
busy: 1 */
447 000000 #define KEYV (0x0002u) /* Flash
Key violation flag */
448 000000 #define ACCVIFG (0x0004u) /* Flash
Access violation flag */
449 000000 #define WAIT (0x0008u) /* Wait
flag for segment write */
450 000000 #define LOCK (0x0010u) /* Lock
bit: 1 - Flash is locked (read only) */
451 000000 #define EMEX (0x0020u) /* Flash
Emergency Exit */
452 000000 #define LOCKA (0x0040u) /*
Segment A Lock bit: read = 1 - Segment is
locked (read only) */
453 000000 #define FAIL (0x0080u) /* Last
Program or Erase failed */
454 000000
455 000000 /***********************************************
*************
456 000000 * DIGITAL I/O Port1/2 Pull up / Pull down
Resistors
457 000000 ************************************************
************/
458 000000 #define __MSP430_HAS_PORT1_R__ /*
Definition to show that Module is available
*/
459 000000 #define __MSP430_HAS_PORT2_R__ /*
Definition to show that Module is available
*/
460 000000
461 000000 #define P1IN_ (0x0020u) /* Port 1
Input */
462 000000 READ_ONLY DEFC( P1IN , P1IN_)
463 000000 #define P1OUT_ (0x0021u) /* Port 1
Output */
464 000000 DEFC( P1OUT , P1OUT_)
465 000000 #define P1DIR_ (0x0022u) /* Port 1
Direction */
466 000000 DEFC( P1DIR , P1DIR_)
467 000000 #define P1IFG_ (0x0023u) /* Port 1
Interrupt Flag */
468 000000 DEFC( P1IFG , P1IFG_)
469 000000 #define P1IES_ (0x0024u) /* Port 1
Interrupt Edge Select */
470 000000 DEFC( P1IES , P1IES_)
471 000000 #define P1IE_ (0x0025u) /* Port 1
Interrupt Enable */
472 000000 DEFC( P1IE , P1IE_)
473 000000 #define P1SEL_ (0x0026u) /* Port 1
Selection */
474 000000 DEFC( P1SEL , P1SEL_)
475 000000 #define P1SEL2_ (0x0041u) /* Port 1
Selection 2 */
476 000000 DEFC( P1SEL2 , P1SEL2_)
477 000000 #define P1REN_ (0x0027u) /* Port 1
Resistor Enable */
478 000000 DEFC( P1REN , P1REN_)
479 000000
480 000000 #define P2IN_ (0x0028u) /* Port 2
Input */
481 000000 READ_ONLY DEFC( P2IN , P2IN_)
482 000000 #define P2OUT_ (0x0029u) /* Port 2
Output */
483 000000 DEFC( P2OUT , P2OUT_)
484 000000 #define P2DIR_ (0x002Au) /* Port 2
Direction */
485 000000 DEFC( P2DIR , P2DIR_)
486 000000 #define P2IFG_ (0x002Bu) /* Port 2
Interrupt Flag */
487 000000 DEFC( P2IFG , P2IFG_)
488 000000 #define P2IES_ (0x002Cu) /* Port 2
Interrupt Edge Select */
489 000000 DEFC( P2IES , P2IES_)
490 000000 #define P2IE_ (0x002Du) /* Port 2
Interrupt Enable */
491 000000 DEFC( P2IE , P2IE_)
492 000000 #define P2SEL_ (0x002Eu) /* Port 2
Selection */
493 000000 DEFC( P2SEL , P2SEL_)
494 000000 #define P2SEL2_ (0x0042u) /* Port 2
Selection 2 */
495 000000 DEFC( P2SEL2 , P2SEL2_)
496 000000 #define P2REN_ (0x002Fu) /* Port 2
Resistor Enable */
497 000000 DEFC( P2REN , P2REN_)
498 000000
499 000000 /***********************************************
*************
500 000000 * DIGITAL I/O Port3 Pull up / Pull down
Resistors
501 000000 ************************************************
************/
502 000000 #define __MSP430_HAS_PORT3_R__ /*
Definition to show that Module is available
*/
503 000000
504 000000 #define P3IN_ (0x0018u) /* Port 3
Input */
505 000000 READ_ONLY DEFC( P3IN , P3IN_)
506 000000 #define P3OUT_ (0x0019u) /* Port 3
Output */
507 000000 DEFC( P3OUT , P3OUT_)
508 000000 #define P3DIR_ (0x001Au) /* Port 3
Direction */
509 000000 DEFC( P3DIR , P3DIR_)
510 000000 #define P3SEL_ (0x001Bu) /* Port 3
Selection */
511 000000 DEFC( P3SEL , P3SEL_)
512 000000 #define P3SEL2_ (0x0043u) /* Port 3
Selection 2 */
513 000000 DEFC( P3SEL2 , P3SEL2_)
514 000000 #define P3REN_ (0x0010u) /* Port 3
Resistor Enable */
515 000000 DEFC( P3REN , P3REN_)
516 000000
517 000000 /***********************************************
*************
518 000000 * Timer0_A3
519 000000 ************************************************
************/
520 000000 #define __MSP430_HAS_TA3__ /*
Definition to show that Module is available
*/
521 000000
522 000000 #define TA0IV_ (0x012Eu) /*
Timer0_A3 Interrupt Vector Word */
523 000000 READ_ONLY DEFW( TA0IV , TA0IV_)
524 000000 #define TA0CTL_ (0x0160u) /*
Timer0_A3 Control */
525 000000 DEFW( TA0CTL , TA0CTL_)
526 000000 #define TA0CCTL0_ (0x0162u) /*
Timer0_A3 Capture/Compare Control 0 */
527 000000 DEFW( TA0CCTL0 , TA0CCTL0_)
528 000000 #define TA0CCTL1_ (0x0164u) /*
Timer0_A3 Capture/Compare Control 1 */
529 000000 DEFW( TA0CCTL1 , TA0CCTL1_)
530 000000 #define TA0CCTL2_ (0x0166u) /*
Timer0_A3 Capture/Compare Control 2 */
531 000000 DEFW( TA0CCTL2 , TA0CCTL2_)
532 000000 #define TA0R_ (0x0170u) /*
Timer0_A3 */
533 000000 DEFW( TA0R , TA0R_)
534 000000 #define TA0CCR0_ (0x0172u) /*
Timer0_A3 Capture/Compare 0 */
535 000000 DEFW( TA0CCR0 , TA0CCR0_)
536 000000 #define TA0CCR1_ (0x0174u) /*
Timer0_A3 Capture/Compare 1 */
537 000000 DEFW( TA0CCR1 , TA0CCR1_)
538 000000 #define TA0CCR2_ (0x0176u) /*
Timer0_A3 Capture/Compare 2 */
539 000000 DEFW( TA0CCR2 , TA0CCR2_)
540 000000
541 000000 /* Alternate register names */
542 000000 #define TAIV TA0IV /* Timer A
Interrupt Vector Word */
543 000000 #define TACTL TA0CTL /* Timer A
Control */
544 000000 #define TACCTL0 TA0CCTL0 /* Timer A
Capture/Compare Control 0 */
545 000000 #define TACCTL1 TA0CCTL1 /* Timer A
Capture/Compare Control 1 */
546 000000 #define TACCTL2 TA0CCTL2 /* Timer A
Capture/Compare Control 2 */
547 000000 #define TAR TA0R /* Timer A
*/
548 000000 #define TACCR0 TA0CCR0 /* Timer A
Capture/Compare 0 */
549 000000 #define TACCR1 TA0CCR1 /* Timer A
Capture/Compare 1 */
550 000000 #define TACCR2 TA0CCR2 /* Timer A
Capture/Compare 2 */
551 000000 #define TAIV_ TA0IV_ /* Timer A
Interrupt Vector Word */
552 000000 #define TACTL_ TA0CTL_ /* Timer A
Control */
553 000000 #define TACCTL0_ TA0CCTL0_ /* Timer A
Capture/Compare Control 0 */
554 000000 #define TACCTL1_ TA0CCTL1_ /* Timer A
Capture/Compare Control 1 */
555 000000 #define TACCTL2_ TA0CCTL2_ /* Timer A
Capture/Compare Control 2 */
556 000000 #define TAR_ TA0R_ /* Timer A
*/
557 000000 #define TACCR0_ TA0CCR0_ /* Timer A
Capture/Compare 0 */
558 000000 #define TACCR1_ TA0CCR1_ /* Timer A
Capture/Compare 1 */
559 000000 #define TACCR2_ TA0CCR2_ /* Timer A
Capture/Compare 2 */
560 000000
561 000000 /* Alternate register names 2 */
562 000000 #define CCTL0 TACCTL0 /* Timer A
Capture/Compare Control 0 */
563 000000 #define CCTL1 TACCTL1 /* Timer A
Capture/Compare Control 1 */
564 000000 #define CCTL2 TACCTL2 /* Timer A
Capture/Compare Control 2 */
565 000000 #define CCR0 TACCR0 /* Timer A
Capture/Compare 0 */
566 000000 #define CCR1 TACCR1 /* Timer A
Capture/Compare 1 */
567 000000 #define CCR2 TACCR2 /* Timer A
Capture/Compare 2 */
568 000000 #define CCTL0_ TACCTL0_ /* Timer A
Capture/Compare Control 0 */
569 000000 #define CCTL1_ TACCTL1_ /* Timer A
Capture/Compare Control 1 */
570 000000 #define CCTL2_ TACCTL2_ /* Timer A
Capture/Compare Control 2 */
571 000000 #define CCR0_ TACCR0_ /* Timer A
Capture/Compare 0 */
572 000000 #define CCR1_ TACCR1_ /* Timer A
Capture/Compare 1 */
573 000000 #define CCR2_ TACCR2_ /* Timer A
Capture/Compare 2 */
574 000000
575 000000 #define TASSEL1 (0x0200u) /* Timer
A clock source select 0 */
576 000000 #define TASSEL0 (0x0100u) /* Timer
A clock source select 1 */
577 000000 #define ID1 (0x0080u) /* Timer
A clock input divider 1 */
578 000000 #define ID0 (0x0040u) /* Timer
A clock input divider 0 */
579 000000 #define MC1 (0x0020u) /* Timer
A mode control 1 */
580 000000 #define MC0 (0x0010u) /* Timer
A mode control 0 */
581 000000 #define TACLR (0x0004u) /* Timer
A counter clear */
582 000000 #define TAIE (0x0002u) /* Timer
A counter interrupt enable */
583 000000 #define TAIFG (0x0001u) /* Timer
A counter interrupt flag */
584 000000
585 000000 #define MC_0 (0*0x10u) /* Timer
A mode control: 0 - Stop */
586 000000 #define MC_1 (1*0x10u) /* Timer
A mode control: 1 - Up to CCR0 */
587 000000 #define MC_2 (2*0x10u) /* Timer
A mode control: 2 - Continous up */
588 000000 #define MC_3 (3*0x10u) /* Timer
A mode control: 3 - Up/Down */
589 000000 #define ID_0 (0*0x40u) /* Timer
A input divider: 0 - /1 */
590 000000 #define ID_1 (1*0x40u) /* Timer
A input divider: 1 - /2 */
591 000000 #define ID_2 (2*0x40u) /* Timer
A input divider: 2 - /4 */
592 000000 #define ID_3 (3*0x40u) /* Timer
A input divider: 3 - /8 */
593 000000 #define TASSEL_0 (0*0x100u) /* Timer
A clock source select: 0 - TACLK */
594 000000 #define TASSEL_1 (1*0x100u) /* Timer
A clock source select: 1 - ACLK */
595 000000 #define TASSEL_2 (2*0x100u) /* Timer
A clock source select: 2 - SMCLK */
596 000000 #define TASSEL_3 (3*0x100u) /* Timer
A clock source select: 3 - INCLK */
597 000000
598 000000 #define CM1 (0x8000u) /*
Capture mode 1 */
599 000000 #define CM0 (0x4000u) /*
Capture mode 0 */
600 000000 #define CCIS1 (0x2000u) /*
Capture input select 1 */
601 000000 #define CCIS0 (0x1000u) /*
Capture input select 0 */
602 000000 #define SCS (0x0800u) /*
Capture sychronize */
603 000000 #define SCCI (0x0400u) /*
Latched capture signal (read) */
604 000000 #define CAP (0x0100u) /*
Capture mode: 1 /Compare mode : 0 */
605 000000 #define OUTMOD2 (0x0080u) /* Output
mode 2 */
606 000000 #define OUTMOD1 (0x0040u) /* Output
mode 1 */
607 000000 #define OUTMOD0 (0x0020u) /* Output
mode 0 */
608 000000 #define CCIE (0x0010u) /*
Capture/compare interrupt enable */
609 000000 #define CCI (0x0008u) /*
Capture input signal (read) */
610 000000 #define OUT (0x0004u) /* PWM
Output signal if output mode 0 */
611 000000 #define COV (0x0002u) /*
Capture/compare overflow flag */
612 000000 #define CCIFG (0x0001u) /*
Capture/compare interrupt flag */
613 000000
614 000000 #define OUTMOD_0 (0*0x20u) /* PWM
output mode: 0 - output only */
615 000000 #define OUTMOD_1 (1*0x20u) /* PWM
output mode: 1 - set */
616 000000 #define OUTMOD_2 (2*0x20u) /* PWM
output mode: 2 - PWM toggle/reset */
617 000000 #define OUTMOD_3 (3*0x20u) /* PWM
output mode: 3 - PWM set/reset */
618 000000 #define OUTMOD_4 (4*0x20u) /* PWM
output mode: 4 - toggle */
619 000000 #define OUTMOD_5 (5*0x20u) /* PWM
output mode: 5 - Reset */
620 000000 #define OUTMOD_6 (6*0x20u) /* PWM
output mode: 6 - PWM toggle/set */
621 000000 #define OUTMOD_7 (7*0x20u) /* PWM
output mode: 7 - PWM reset/set */
622 000000 #define CCIS_0 (0*0x1000u) /*
Capture input select: 0 - CCIxA */
623 000000 #define CCIS_1 (1*0x1000u) /*
Capture input select: 1 - CCIxB */
624 000000 #define CCIS_2 (2*0x1000u) /*
Capture input select: 2 - GND */
625 000000 #define CCIS_3 (3*0x1000u) /*
Capture input select: 3 - Vcc */
626 000000 #define CM_0 (0*0x4000u) /*
Capture mode: 0 - disabled */
627 000000 #define CM_1 (1*0x4000u) /*
Capture mode: 1 - pos. edge */
628 000000 #define CM_2 (2*0x4000u) /*
Capture mode: 1 - neg. edge */
629 000000 #define CM_3 (3*0x4000u) /*
Capture mode: 1 - both edges */
630 000000
631 000000 /* T0_A3IV Definitions */
632 000000 #define TA0IV_NONE (0x0000u) /* No
Interrupt pending */
633 000000 #define TA0IV_TACCR1 (0x0002u) /*
TA0CCR1_CCIFG */
634 000000 #define TA0IV_TACCR2 (0x0004u) /*
TA0CCR2_CCIFG */
635 000000 #define TA0IV_6 (0x0006u) /*
Reserved */
636 000000 #define TA0IV_8 (0x0008u) /*
Reserved */
637 000000 #define TA0IV_TAIFG (0x000Au) /*
TA0IFG */
638 000000
639 000000 /***********************************************
*************
640 000000 * Timer1_A3
641 000000 ************************************************
************/
642 000000 #define __MSP430_HAS_T1A3__ /*
Definition to show that Module is available
*/
643 000000
644 000000 #define TA1IV_ (0x011Eu) /*
Timer1_A3 Interrupt Vector Word */
645 000000 READ_ONLY DEFW( TA1IV , TA1IV_)
646 000000 #define TA1CTL_ (0x0180u) /*
Timer1_A3 Control */
647 000000 DEFW( TA1CTL , TA1CTL_)
648 000000 #define TA1CCTL0_ (0x0182u) /*
Timer1_A3 Capture/Compare Control 0 */
649 000000 DEFW( TA1CCTL0 , TA1CCTL0_)
650 000000 #define TA1CCTL1_ (0x0184u) /*
Timer1_A3 Capture/Compare Control 1 */
651 000000 DEFW( TA1CCTL1 , TA1CCTL1_)
652 000000 #define TA1CCTL2_ (0x0186u) /*
Timer1_A3 Capture/Compare Control 2 */
653 000000 DEFW( TA1CCTL2 , TA1CCTL2_)
654 000000 #define TA1R_ (0x0190u) /*
Timer1_A3 */
655 000000 DEFW( TA1R , TA1R_)
656 000000 #define TA1CCR0_ (0x0192u) /*
Timer1_A3 Capture/Compare 0 */
657 000000 DEFW( TA1CCR0 , TA1CCR0_)
658 000000 #define TA1CCR1_ (0x0194u) /*
Timer1_A3 Capture/Compare 1 */
659 000000 DEFW( TA1CCR1 , TA1CCR1_)
660 000000 #define TA1CCR2_ (0x0196u) /*
Timer1_A3 Capture/Compare 2 */
661 000000 DEFW( TA1CCR2 , TA1CCR2_)
662 000000
663 000000 /* Bits are already defined within the Timer0_Ax
*/
664 000000
665 000000 /* T1_A3IV Definitions */
666 000000 #define TA1IV_NONE (0x0000u) /* No
Interrupt pending */
667 000000 #define TA1IV_TACCR1 (0x0002u) /*
TA1CCR1_CCIFG */
668 000000 #define TA1IV_TACCR2 (0x0004u) /*
TA1CCR2_CCIFG */
669 000000 #define TA1IV_TAIFG (0x000Au) /*
TA1IFG */
670 000000
671 000000 /***********************************************
*************
672 000000 * USCI
673 000000 ************************************************
************/
674 000000 #define __MSP430_HAS_USCI__ /*
Definition to show that Module is available
*/
675 000000
676 000000 #define UCA0CTL0_ (0x0060u) /* USCI
A0 Control Register 0 */
677 000000 DEFC( UCA0CTL0 , UCA0CTL0_)
678 000000 #define UCA0CTL1_ (0x0061u) /* USCI
A0 Control Register 1 */
679 000000 DEFC( UCA0CTL1 , UCA0CTL1_)
680 000000 #define UCA0BR0_ (0x0062u) /* USCI
A0 Baud Rate 0 */
681 000000 DEFC( UCA0BR0 , UCA0BR0_)
682 000000 #define UCA0BR1_ (0x0063u) /* USCI
A0 Baud Rate 1 */
683 000000 DEFC( UCA0BR1 , UCA0BR1_)
684 000000 #define UCA0MCTL_ (0x0064u) /* USCI
A0 Modulation Control */
685 000000 DEFC( UCA0MCTL , UCA0MCTL_)
686 000000 #define UCA0STAT_ (0x0065u) /* USCI
A0 Status Register */
687 000000 DEFC( UCA0STAT , UCA0STAT_)
688 000000 #define UCA0RXBUF_ (0x0066u) /* USCI
A0 Receive Buffer */
689 000000 READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_)
690 000000 #define UCA0TXBUF_ (0x0067u) /* USCI
A0 Transmit Buffer */
691 000000 DEFC( UCA0TXBUF , UCA0TXBUF_)
692 000000 #define UCA0ABCTL_ (0x005Du) /* USCI
A0 LIN Control */
693 000000 DEFC( UCA0ABCTL , UCA0ABCTL_)
694 000000 #define UCA0IRTCTL_ (0x005Eu) /* USCI
A0 IrDA Transmit Control */
695 000000 DEFC( UCA0IRTCTL , UCA0IRTCTL_)
696 000000 #define UCA0IRRCTL_ (0x005Fu) /* USCI
A0 IrDA Receive Control */
697 000000 DEFC( UCA0IRRCTL , UCA0IRRCTL_)
698 000000
699 000000
700 000000
701 000000 #define UCB0CTL0_ (0x0068u) /* USCI
B0 Control Register 0 */
702 000000 DEFC( UCB0CTL0 , UCB0CTL0_)
703 000000 #define UCB0CTL1_ (0x0069u) /* USCI
B0 Control Register 1 */
704 000000 DEFC( UCB0CTL1 , UCB0CTL1_)
705 000000 #define UCB0BR0_ (0x006Au) /* USCI
B0 Baud Rate 0 */
706 000000 DEFC( UCB0BR0 , UCB0BR0_)
707 000000 #define UCB0BR1_ (0x006Bu) /* USCI
B0 Baud Rate 1 */
708 000000 DEFC( UCB0BR1 , UCB0BR1_)
709 000000 #define UCB0I2CIE_ (0x006Cu) /* USCI
B0 I2C Interrupt Enable Register */
710 000000 DEFC( UCB0I2CIE , UCB0I2CIE_)
711 000000 #define UCB0STAT_ (0x006Du) /* USCI
B0 Status Register */
712 000000 DEFC( UCB0STAT , UCB0STAT_)
713 000000 #define UCB0RXBUF_ (0x006Eu) /* USCI
B0 Receive Buffer */
714 000000 READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_)
715 000000 #define UCB0TXBUF_ (0x006Fu) /* USCI
B0 Transmit Buffer */
716 000000 DEFC( UCB0TXBUF , UCB0TXBUF_)
717 000000 #define UCB0I2COA_ (0x0118u) /* USCI
B0 I2C Own Address */
718 000000 DEFW( UCB0I2COA , UCB0I2COA_)
719 000000 #define UCB0I2CSA_ (0x011Au) /* USCI
B0 I2C Slave Address */
720 000000 DEFW( UCB0I2CSA , UCB0I2CSA_)
721 000000
722 000000 // UART-Mode Bits
723 000000 #define UCPEN (0x80) /* Async.
Mode: Parity enable */
724 000000 #define UCPAR (0x40) /* Async.
Mode: Parity 0:odd / 1:even */
725 000000 #define UCMSB (0x20) /* Async.
Mode: MSB first 0:LSB / 1:MSB */
726 000000 #define UC7BIT (0x10) /* Async.
Mode: Data Bits 0:8-bits / 1:7-bits */
727 000000 #define UCSPB (0x08) /* Async.
Mode: Stop Bits 0:one / 1: two */
728 000000 #define UCMODE1 (0x04) /* Async.
Mode: USCI Mode 1 */
729 000000 #define UCMODE0 (0x02) /* Async.
Mode: USCI Mode 0 */
730 000000 #define UCSYNC (0x01) /*
Sync-Mode 0:UART-Mode / 1:SPI-Mode */
731 000000
732 000000 // SPI-Mode Bits
733 000000 #define UCCKPH (0x80) /* Sync.
Mode: Clock Phase */
734 000000 #define UCCKPL (0x40) /* Sync.
Mode: Clock Polarity */
735 000000 #define UCMST (0x08) /* Sync.
Mode: Master Select */
736 000000
737 000000 // I2C-Mode Bits
738 000000 #define UCA10 (0x80) /* 10-bit
Address Mode */
739 000000 #define UCSLA10 (0x40) /* 10-bit
Slave Address Mode */
740 000000 #define UCMM (0x20) /*
Multi-Master Environment */
741 000000 //#define res (0x10) /*
reserved */
742 000000 #define UCMODE_0 (0x00) /* Sync.
Mode: USCI Mode: 0 */
743 000000 #define UCMODE_1 (0x02) /* Sync.
Mode: USCI Mode: 1 */
744 000000 #define UCMODE_2 (0x04) /* Sync.
Mode: USCI Mode: 2 */
745 000000 #define UCMODE_3 (0x06) /* Sync.
Mode: USCI Mode: 3 */
746 000000
747 000000 // UART-Mode Bits
748 000000 #define UCSSEL1 (0x80) /* USCI 0
Clock Source Select 1 */
749 000000 #define UCSSEL0 (0x40) /* USCI 0
Clock Source Select 0 */
750 000000 #define UCRXEIE (0x20) /* RX
Error interrupt enable */
751 000000 #define UCBRKIE (0x10) /* Break
interrupt enable */
752 000000 #define UCDORM (0x08) /* Dormant
(Sleep) Mode */
753 000000 #define UCTXADDR (0x04) /* Send
next Data as Address */
754 000000 #define UCTXBRK (0x02) /* Send
next Data as Break */
755 000000 #define UCSWRST (0x01) /* USCI
Software Reset */
756 000000
757 000000 // SPI-Mode Bits
758 000000 //#define res (0x20) /*
reserved */
759 000000 //#define res (0x10) /*
reserved */
760 000000 //#define res (0x08) /*
reserved */
761 000000 //#define res (0x04) /*
reserved */
762 000000 //#define res (0x02) /*
reserved */
763 000000
764 000000 // I2C-Mode Bits
765 000000 //#define res (0x20) /*
reserved */
766 000000 #define UCTR (0x10) /*
Transmit/Receive Select/Flag */
767 000000 #define UCTXNACK (0x08) /*
Transmit NACK */
768 000000 #define UCTXSTP (0x04) /*
Transmit STOP */
769 000000 #define UCTXSTT (0x02) /*
Transmit START */
770 000000 #define UCSSEL_0 (0x00) /* USCI 0
Clock Source: 0 */
771 000000 #define UCSSEL_1 (0x40) /* USCI 0
Clock Source: 1 */
772 000000 #define UCSSEL_2 (0x80) /* USCI 0
Clock Source: 2 */
773 000000 #define UCSSEL_3 (0xC0) /* USCI 0
Clock Source: 3 */
774 000000
775 000000 #define UCBRF3 (0x80) /* USCI
First Stage Modulation Select 3 */
776 000000 #define UCBRF2 (0x40) /* USCI
First Stage Modulation Select 2 */
777 000000 #define UCBRF1 (0x20) /* USCI
First Stage Modulation Select 1 */
778 000000 #define UCBRF0 (0x10) /* USCI
First Stage Modulation Select 0 */
779 000000 #define UCBRS2 (0x08) /* USCI
Second Stage Modulation Select 2 */
780 000000 #define UCBRS1 (0x04) /* USCI
Second Stage Modulation Select 1 */
781 000000 #define UCBRS0 (0x02) /* USCI
Second Stage Modulation Select 0 */
782 000000 #define UCOS16 (0x01) /* USCI
16-times Oversampling enable */
783 000000
784 000000 #define UCBRF_0 (0x00) /* USCI
First Stage Modulation: 0 */
785 000000 #define UCBRF_1 (0x10) /* USCI
First Stage Modulation: 1 */
786 000000 #define UCBRF_2 (0x20) /* USCI
First Stage Modulation: 2 */
787 000000 #define UCBRF_3 (0x30) /* USCI
First Stage Modulation: 3 */
788 000000 #define UCBRF_4 (0x40) /* USCI
First Stage Modulation: 4 */
789 000000 #define UCBRF_5 (0x50) /* USCI
First Stage Modulation: 5 */
790 000000 #define UCBRF_6 (0x60) /* USCI
First Stage Modulation: 6 */
791 000000 #define UCBRF_7 (0x70) /* USCI
First Stage Modulation: 7 */
792 000000 #define UCBRF_8 (0x80) /* USCI
First Stage Modulation: 8 */
793 000000 #define UCBRF_9 (0x90) /* USCI
First Stage Modulation: 9 */
794 000000 #define UCBRF_10 (0xA0) /* USCI
First Stage Modulation: A */
795 000000 #define UCBRF_11 (0xB0) /* USCI
First Stage Modulation: B */
796 000000 #define UCBRF_12 (0xC0) /* USCI
First Stage Modulation: C */
797 000000 #define UCBRF_13 (0xD0) /* USCI
First Stage Modulation: D */
798 000000 #define UCBRF_14 (0xE0) /* USCI
First Stage Modulation: E */
799 000000 #define UCBRF_15 (0xF0) /* USCI
First Stage Modulation: F */
800 000000
801 000000 #define UCBRS_0 (0x00) /* USCI
Second Stage Modulation: 0 */
802 000000 #define UCBRS_1 (0x02) /* USCI
Second Stage Modulation: 1 */
803 000000 #define UCBRS_2 (0x04) /* USCI
Second Stage Modulation: 2 */
804 000000 #define UCBRS_3 (0x06) /* USCI
Second Stage Modulation: 3 */
805 000000 #define UCBRS_4 (0x08) /* USCI
Second Stage Modulation: 4 */
806 000000 #define UCBRS_5 (0x0A) /* USCI
Second Stage Modulation: 5 */
807 000000 #define UCBRS_6 (0x0C) /* USCI
Second Stage Modulation: 6 */
808 000000 #define UCBRS_7 (0x0E) /* USCI
Second Stage Modulation: 7 */
809 000000
810 000000 #define UCLISTEN (0x80) /* USCI
Listen mode */
811 000000 #define UCFE (0x40) /* USCI
Frame Error Flag */
812 000000 #define UCOE (0x20) /* USCI
Overrun Error Flag */
813 000000 #define UCPE (0x10) /* USCI
Parity Error Flag */
814 000000 #define UCBRK (0x08) /* USCI
Break received */
815 000000 #define UCRXERR (0x04) /* USCI RX
Error Flag */
816 000000 #define UCADDR (0x02) /* USCI
Address received Flag */
817 000000 #define UCBUSY (0x01) /* USCI
Busy Flag */
818 000000 #define UCIDLE (0x02) /* USCI
Idle line detected Flag */
819 000000
820 000000 //#define res (0x80) /*
reserved */
821 000000 //#define res (0x40) /*
reserved */
822 000000 //#define res (0x20) /*
reserved */
823 000000 //#define res (0x10) /*
reserved */
824 000000 #define UCNACKIE (0x08) /* NACK
Condition interrupt enable */
825 000000 #define UCSTPIE (0x04) /* STOP
Condition interrupt enable */
826 000000 #define UCSTTIE (0x02) /* START
Condition interrupt enable */
827 000000 #define UCALIE (0x01) /*
Arbitration Lost interrupt enable */
828 000000
829 000000 #define UCSCLLOW (0x40) /* SCL low
*/
830 000000 #define UCGC (0x20) /* General
Call address received Flag */
831 000000 #define UCBBUSY (0x10) /* Bus
Busy Flag */
832 000000 #define UCNACKIFG (0x08) /* NAK
Condition interrupt Flag */
833 000000 #define UCSTPIFG (0x04) /* STOP
Condition interrupt Flag */
834 000000 #define UCSTTIFG (0x02) /* START
Condition interrupt Flag */
835 000000 #define UCALIFG (0x01) /*
Arbitration Lost interrupt Flag */
836 000000
837 000000 #define UCIRTXPL5 (0x80) /* IRDA
Transmit Pulse Length 5 */
838 000000 #define UCIRTXPL4 (0x40) /* IRDA
Transmit Pulse Length 4 */
839 000000 #define UCIRTXPL3 (0x20) /* IRDA
Transmit Pulse Length 3 */
840 000000 #define UCIRTXPL2 (0x10) /* IRDA
Transmit Pulse Length 2 */
841 000000 #define UCIRTXPL1 (0x08) /* IRDA
Transmit Pulse Length 1 */
842 000000 #define UCIRTXPL0 (0x04) /* IRDA
Transmit Pulse Length 0 */
843 000000 #define UCIRTXCLK (0x02) /* IRDA
Transmit Pulse Clock Select */
844 000000 #define UCIREN (0x01) /* IRDA
Encoder/Decoder enable */
845 000000
846 000000 #define UCIRRXFL5 (0x80) /* IRDA
Receive Filter Length 5 */
847 000000 #define UCIRRXFL4 (0x40) /* IRDA
Receive Filter Length 4 */
848 000000 #define UCIRRXFL3 (0x20) /* IRDA
Receive Filter Length 3 */
849 000000 #define UCIRRXFL2 (0x10) /* IRDA
Receive Filter Length 2 */
850 000000 #define UCIRRXFL1 (0x08) /* IRDA
Receive Filter Length 1 */
851 000000 #define UCIRRXFL0 (0x04) /* IRDA
Receive Filter Length 0 */
852 000000 #define UCIRRXPL (0x02) /* IRDA
Receive Input Polarity */
853 000000 #define UCIRRXFE (0x01) /* IRDA
Receive Filter enable */
854 000000
855 000000 //#define res (0x80) /*
reserved */
856 000000 //#define res (0x40) /*
reserved */
857 000000 #define UCDELIM1 (0x20) /* Break
Sync Delimiter 1 */
858 000000 #define UCDELIM0 (0x10) /* Break
Sync Delimiter 0 */
859 000000 #define UCSTOE (0x08) /*
Sync-Field Timeout error */
860 000000 #define UCBTOE (0x04) /* Break
Timeout error */
861 000000 //#define res (0x02) /*
reserved */
862 000000 #define UCABDEN (0x01) /* Auto
Baud Rate detect enable */
863 000000
864 000000 #define UCGCEN (0x8000u) /* I2C
General Call enable */
865 000000 #define UCOA9 (0x0200u) /* I2C
Own Address 9 */
866 000000 #define UCOA8 (0x0100u) /* I2C
Own Address 8 */
867 000000 #define UCOA7 (0x0080u) /* I2C
Own Address 7 */
868 000000 #define UCOA6 (0x0040u) /* I2C
Own Address 6 */
869 000000 #define UCOA5 (0x0020u) /* I2C
Own Address 5 */
870 000000 #define UCOA4 (0x0010u) /* I2C
Own Address 4 */
871 000000 #define UCOA3 (0x0008u) /* I2C
Own Address 3 */
872 000000 #define UCOA2 (0x0004u) /* I2C
Own Address 2 */
873 000000 #define UCOA1 (0x0002u) /* I2C
Own Address 1 */
874 000000 #define UCOA0 (0x0001u) /* I2C
Own Address 0 */
875 000000
876 000000 #define UCSA9 (0x0200u) /* I2C
Slave Address 9 */
877 000000 #define UCSA8 (0x0100u) /* I2C
Slave Address 8 */
878 000000 #define UCSA7 (0x0080u) /* I2C
Slave Address 7 */
879 000000 #define UCSA6 (0x0040u) /* I2C
Slave Address 6 */
880 000000 #define UCSA5 (0x0020u) /* I2C
Slave Address 5 */
881 000000 #define UCSA4 (0x0010u) /* I2C
Slave Address 4 */
882 000000 #define UCSA3 (0x0008u) /* I2C
Slave Address 3 */
883 000000 #define UCSA2 (0x0004u) /* I2C
Slave Address 2 */
884 000000 #define UCSA1 (0x0002u) /* I2C
Slave Address 1 */
885 000000 #define UCSA0 (0x0001u) /* I2C
Slave Address 0 */
886 000000
887 000000 /***********************************************
*************
888 000000 * WATCHDOG TIMER
889 000000 ************************************************
************/
890 000000 #define __MSP430_HAS_WDT__ /*
Definition to show that Module is available
*/
891 000000
892 000000 #define WDTCTL_ (0x0120u) /*
Watchdog Timer Control */
893 000000 DEFW( WDTCTL , WDTCTL_)
894 000000 /* The bit names have been prefixed with "WDT"
*/
895 000000 #define WDTIS0 (0x0001u)
896 000000 #define WDTIS1 (0x0002u)
897 000000 #define WDTSSEL (0x0004u)
898 000000 #define WDTCNTCL (0x0008u)
899 000000 #define WDTTMSEL (0x0010u)
900 000000 #define WDTNMI (0x0020u)
901 000000 #define WDTNMIES (0x0040u)
902 000000 #define WDTHOLD (0x0080u)
903 000000
904 000000 #define WDTPW (0x5A00u)
905 000000
906 000000 /* WDT-interval times [1ms] coded with Bits 0-2
*/
907 000000 /* WDT is clocked by fSMCLK (assumed 1MHz)
*/
908 000000 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTC
NTCL) /* 32ms interval
(default) */
909 000000 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTIS0) /* 8ms "
*/
910 000000 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTIS1) /* 0.5ms "
*/
911 000000 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTIS1+WDTIS0) /* 0.064ms "
*/
912 000000 /* WDT is clocked by fACLK (assumed 32KHz)
*/
913 000000 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL) /* 1000ms "
*/
914 000000 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL+WDTIS0) /* 250ms "
*/
915 000000 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL+WDTIS1) /* 16ms "
*/
916 000000 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms "
*/
917 000000 /* Watchdog mode -> reset after expired time
*/
918 000000 /* WDT is clocked by fSMCLK (assumed 1MHz)
*/
919 000000 #define WDT_MRST_32 (WDTPW+WDTCNTCL)
/* 32ms interval
(default) */
920 000000 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTI
S0) /* 8ms "
*/
921 000000 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTI
S1) /* 0.5ms "
*/
922 000000 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTI
S1+WDTIS0) /* 0.064ms "
*/
923 000000 /* WDT is clocked by fACLK (assumed 32KHz)
*/
924 000000 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTS
SEL) /* 1000ms "
*/
925 000000 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTS
SEL+WDTIS0) /* 250ms "
*/
926 000000 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTS
SEL+WDTIS1) /* 16ms "
*/
927 000000 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTS
SEL+WDTIS1+WDTIS0) /* 1.9ms "
*/
928 000000
929 000000 /* INTERRUPT CONTROL */
930 000000 /* These two bits are defined in the Special
Function Registers */
931 000000 /* #define WDTIE 0x01 */
932 000000 /* #define WDTIFG 0x01 */
933 000000
934 000000 /***********************************************
*************
935 000000 * Calibration Data in Info Mem
936 000000 ************************************************
************/
937 000000
938 000000 #ifndef __DisableCalData
939 000000
940 000000 #define CALDCO_16MHZ_ (0x10F8u) /*
DCOCTL Calibration Data for 16MHz */
941 000000 READ_ONLY DEFC( CALDCO_16MHZ , CALDCO_16MHZ_
)
942 000000 #define CALBC1_16MHZ_ (0x10F9u) /*
BCSCTL1 Calibration Data for 16MHz */
943 000000 READ_ONLY DEFC( CALBC1_16MHZ , CALBC1_16MHZ_
)
944 000000 #define CALDCO_12MHZ_ (0x10FAu) /*
DCOCTL Calibration Data for 12MHz */
945 000000 READ_ONLY DEFC( CALDCO_12MHZ , CALDCO_12MHZ_
)
946 000000 #define CALBC1_12MHZ_ (0x10FBu) /*
BCSCTL1 Calibration Data for 12MHz */
947 000000 READ_ONLY DEFC( CALBC1_12MHZ , CALBC1_12MHZ_
)
948 000000 #define CALDCO_8MHZ_ (0x10FCu) /*
DCOCTL Calibration Data for 8MHz */
949 000000 READ_ONLY DEFC( CALDCO_8MHZ , CALDCO_8MHZ_)
950 000000 #define CALBC1_8MHZ_ (0x10FDu) /*
BCSCTL1 Calibration Data for 8MHz */
951 000000 READ_ONLY DEFC( CALBC1_8MHZ , CALBC1_8MHZ_)
952 000000 #define CALDCO_1MHZ_ (0x10FEu) /*
DCOCTL Calibration Data for 1MHz */
953 000000 READ_ONLY DEFC( CALDCO_1MHZ , CALDCO_1MHZ_)
954 000000 #define CALBC1_1MHZ_ (0x10FFu) /*
BCSCTL1 Calibration Data for 1MHz */
955 000000 READ_ONLY DEFC( CALBC1_1MHZ , CALBC1_1MHZ_)
956 000000
957 000000 #endif /* #ifndef __DisableCalData */
958 000000
959 000000 /***********************************************
*************
960 000000 * Interrupt Vectors (offset from 0xFFE0)
961 000000 ************************************************
************/
962 000000
963 000000 #define PORT1_VECTOR (2 * 2u) /* 0xFFE4
Port 1 */
964 000000 #define PORT2_VECTOR (3 * 2u) /* 0xFFE6
Port 2 */
965 000000 #define ADC10_VECTOR (5 * 2u) /* 0xFFEA
ADC10 */
966 000000 #define USCIAB0TX_VECTOR (6 * 2u) /* 0xFFEC
USCI A0/B0 Transmit */
967 000000 #define USCIAB0RX_VECTOR (7 * 2u) /* 0xFFEE
USCI A0/B0 Receive */
968 000000 #define TIMER0_A1_VECTOR (8 * 2u) /* 0xFFF0
Timer0)A CC1, TA0 */
969 000000 #define TIMER0_A0_VECTOR (9 * 2u) /* 0xFFF2
Timer0_A CC0 */
970 000000 #define WDT_VECTOR (10 * 2u) /* 0xFFF4
Watchdog Timer */
971 000000 #define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6
Comparator A */
972 000000 #define TIMER1_A1_VECTOR (12 * 2u) /* 0xFFF8
Timer1_A CC1-4, TA1 */
973 000000 #define TIMER1_A0_VECTOR (13 * 2u) /* 0xFFFA
Timer1_A CC0 */
974 000000 #define NMI_VECTOR (14 * 2u) /* 0xFFFC
Non-maskable */
975 000000 #define RESET_VECTOR (15 * 2u) /* 0xFFFE
Reset [Highest Priority] */
976 000000
977 000000 /***********************************************
*************
978 000000 * End of Modules
979 000000 ************************************************
************/
980 000000 #pragma language=default
981 000000
982 000000 #endif /* #ifndef __MSP430G2553 */
983 000000
986 000000
987 000000 #elif defined (__MSP430G2203__)
988 000000 #include "msp430g2203.h"
990 000000 #elif defined (__MSP430G2303__)
991 000000 #include "msp430g2303.h"
993 000000 #elif defined (__MSP430G2403__)
994 000000 #include "msp430g2403.h"
996 000000 #elif defined (__MSP430G2233__)
997 000000 #include "msp430g2233.h"
999 000000 #elif defined (__MSP430G2333__)
1000 000000 #include "msp430g2333.h"
1002 000000 #elif defined (__MSP430G2433__)
1003 000000 #include "msp430g2433.h"
1005 000000 #elif defined (__MSP430G2533__)
1006 000000 #include "msp430g2533.h"
1008 000000 #elif defined (__MSP430BT5190__)
1009 000000 #include "msp430bt5190.h"
1014 000000 #elif defined (__MSP430GENERIC__)
1015 000000 #error "msp430 generic device does not have a
default include file"
1017 000000 #elif defined (__MSP430XGENERIC__)
1018 000000 #error "msp430X generic device does not have a
default include file"
1024 000000 #else
1025 000000 #error "Failed to match a default include
file"
1026 000000 #endif
1027 000000
1028 000000 #endif /* #ifndef __msp430 */
1029 000000
25 000000 #include "4e-CF430G2553forth.h" ;
header macros and register defs
1 000000 ; ----------------------------------------------
------------------------
2 000000 ; 4e4th is a Forth based on CamelForth
3 000000 ; for the Texas Instruments MSP430
4 000000 ;
5 000000 ; This program is free software; you can
redistribute it and/or modify
6 000000 ; it under the terms of the GNU General Public
License as published by
7 000000 ; the Free Software Foundation; either version 3
of the License, or
8 000000 ; (at your option) any later version.
9 000000 ;
10 000000 ; This program is distributed in the hope that
it will be useful,
11 000000 ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 000000 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 000000 ; GNU General Public License for more details.
14 000000 ;
15 000000 ; You should have received a copy of the GNU
General Public License
16 000000 ; along with this program. If not, see
.
17 000000 ;
18 000000 ; See LICENSE TERMS in Brads file readme.txt as
well.
19 000000
20 000000 ; ----------------------------------------------
------------------------
21 000000 ; 4e-CF430G2553forth.h: - Register, Model, Macro
declarations - MSP430G2553
22 000000 ; ----------------------------------------------
------------------------
23 000000
24 000000 // ; FORTH MEMORY USAGE
25 000000 // ; for Flash memory operations - this includes
information and main
26 000000 // ; ROM, but not the main ROM used by the
kernel (above E000h)
27 000000 #define INFOSTART (0x1000) // ok mk
28 000000 #define INFOEND (0x10FF) // ok mk
29 000000 #define RAMSTART (0x0200) // ok mk
30 000000 #define RAMEND (0x03FF) // ok mk
31 000000 #define FLASHSTART (0xC000) // ok mk
32 000000 #define FLASHEND (0xDFFF) // ok mk
33 000000 #define MAINSEG (512) // wozu ?? mk
34 000000 #define INFOSEG (128) // ?? mk
35 000000
36 000000 // ; FORTH REGISTER USAGE
37 000000
38 000000 // ; Forth virtual machine
39 000000 #define RSP SP
40 000000 #define PSP R4
41 000000 #define IP R5
42 000000 #define W R6
43 000000 #define TOS R7
44 000000
45 000000 // ; Loop parameters in registers
46 000000 #define INDEX R8
47 000000 #define LIMIT R9
48 000000
49 000000 // ; Scratch registers
50 000000 #define X R10
51 000000 #define Y R11
52 000000 #define Q R12
53 000000 #define T R13
54 000000
55 000000 // ; T.I. Integer Subroutines Definitions
56 000000 #define IROP1 TOS
57 000000 #define IROP2L R10
58 000000 #define IROP2M R11
59 000000 #define IRACL R12
60 000000 #define IRACM R13
61 000000 #define IRBT W
62 000000
63 000000 // ; INDIRECT-THREADED NEXT
64 000000
69 000000
70 000000 // ; BRANCH DESTINATION (RELATIVE BRANCH)
71 000000 // ; For relative branch addresses, i.e., a
branch is ADD @IP,IP
72 000000
76 000000
77 000000 // ; HEADER CONSTRUCTION MACROS
78 000000
93 000000
102 000000
117 000000
26 000000
27 000000 EXTERN RAMDICT,lastword,NOOP,DOTCOLD
28 000000 PUBLIC infoB,AppU0,crcval
29 000000
30 000000 RSEG INFOB
31 000000
32 000000 ; uarea in infoB - holds saved user area
table
33 000000
34 000000 infoB:
35 000000 FFFF crcval: DW 0FFFFh ; CRC of user dictionary
and infoB user
area
36 000002 000000000A00*AppU0: DW 0,0,10,0 ; reserved,>IN,BASE,STAT
E ; start in HEX
mk
37 00000A .... DW RAMDICT ; DP
38 00000C 00000000 DW 0,0 ; SOURCE init'd
elsewhere
39 000010 .... DW lastword ; LATEST
40 000012 00000000 DW 0,0 ; HP,LP init'd
elsewhere
41 000016 00C0 DW FLASHSTART ; IDP
42 000018 0000 DW 0 ; NEWEST not init'd
43 00001A .... DW DOTCOLD ; app
44 00001C FFFF DW -1 ; CAPS ON
45 00001E 00000000 DW 0,0 ; user variables
TBD
46 000022
47 000022 END
ACCVIE #define, value: (0x20), line: 132:2
ACCVIFG #define, value: (0x0004u), line: 448:2
ADC10AE0_ #define, value: (0x004Au), line: 167:2 168:2
ADC10B1 #define, value: (0x002), line: 271:2
ADC10BUSY #define, value: (0x0001u), line: 211:2
ADC10CT #define, value: (0x004), line: 272:2
ADC10CTL0_ #define, value: (0x01B0u), line: 170:2 171:2
ADC10CTL1_ #define, value: (0x01B2u), line: 172:2 173:2
ADC10DF #define, value: (0x0200u), line: 220:2
ADC10DISABLE #define, value: (0x000), line: 274:2
ADC10DIV0 #define, value: (0x0020u), line: 216:2
ADC10DIV1 #define, value: (0x0040u), line: 217:2
ADC10DIV2 #define, value: (0x0080u), line: 218:2
ADC10DIV_0 #define, value: (0*0x20u), line: 238:2
ADC10DIV_1 #define, value: (1*0x20u), line: 239:2
ADC10DIV_2 #define, value: (2*0x20u), line: 240:2
ADC10DIV_3 #define, value: (3*0x20u), line: 241:2
ADC10DIV_4 #define, value: (4*0x20u), line: 242:2
ADC10DIV_5 #define, value: (5*0x20u), line: 243:2
ADC10DIV_6 #define, value: (6*0x20u), line: 244:2
ADC10DIV_7 #define, value: (7*0x20u), line: 245:2
ADC10DTC0_ #define, value: (0x0048u), line: 163:2 164:2
ADC10DTC1_ #define, value: (0x0049u), line: 165:2 166:2
ADC10FETCH #define, value: (0x001), line: 270:2
ADC10IE #define, value: (0x008), line: 183:2
ADC10IFG #define, value: (0x004), line: 182:2
ADC10MEM_ #define, value: (0x01B4u), line: 174:2 175:2
ADC10ON #define, value: (0x010), line: 184:2
ADC10SA_ #define, value: (0x01BCu), line: 176:2 177:2
ADC10SC #define, value: (0x001), line: 180:2
ADC10SHT0 #define, value: (0x800), line: 191:2
ADC10SHT1 #define, value: (0x1000u), line: 192:2
ADC10SHT_0 #define, value: (0*0x800u), line: 196:2
ADC10SHT_1 #define, value: (1*0x800u), line: 197:2
ADC10SHT_2 #define, value: (2*0x800u), line: 198:2
ADC10SHT_3 #define, value: (3*0x800u), line: 199:2
ADC10SR #define, value: (0x400), line: 190:2
ADC10SSEL0 #define, value: (0x0008u), line: 214:2
ADC10SSEL1 #define, value: (0x0010u), line: 215:2
ADC10SSEL_0 #define, value: (0*8u), line: 233:2
ADC10SSEL_1 #define, value: (1*8u), line: 234:2
ADC10SSEL_2 #define, value: (2*8u), line: 235:2
ADC10SSEL_3 #define, value: (3*8u), line: 236:2
ADC10TB #define, value: (0x008), line: 273:2
ADC10_VECTOR #define, value: (5 * 2u), line: 965:2
BCSCTL1_ #define, value: (0x0057u), line: 283:2 284:2
BCSCTL2_ #define, value: (0x0058u), line: 285:2 286:2
BCSCTL3_ #define, value: (0x0053u), line: 287:2 288:2
BIT0 #define, value: (0x0001u), line: 57:2
BIT1 #define, value: (0x0002u), line: 58:2
BIT2 #define, value: (0x0004u), line: 59:2
BIT3 #define, value: (0x0008u), line: 60:2
BIT4 #define, value: (0x0010u), line: 61:2
BIT5 #define, value: (0x0020u), line: 62:2
BIT6 #define, value: (0x0040u), line: 63:2
BIT7 #define, value: (0x0080u), line: 64:2
BIT8 #define, value: (0x0100u), line: 65:2
BIT9 #define, value: (0x0200u), line: 66:2
BITA #define, value: (0x0400u), line: 67:2
BITB #define, value: (0x0800u), line: 68:2
BITC #define, value: (0x1000u), line: 69:2
BITD #define, value: (0x2000u), line: 70:2
BITE #define, value: (0x4000u), line: 71:2
BITF #define, value: (0x8000u), line: 72:2
BLKWRT #define, value: (0x0080u), line: 423:2
BUSY #define, value: (0x0001u), line: 446:2
C #define, value: (0x0001u), line: 78:2
CACTL1_ #define, value: (0x0059u), line: 365:2 366:2
CACTL2_ #define, value: (0x005Au), line: 367:2 368:2
CAEX #define, value: (0x80), line: 379:2
CAF #define, value: (0x02), line: 387:2
CAIE #define, value: (0x02), line: 373:2
CAIES #define, value: (0x04), line: 374:2
CAIFG #define, value: (0x01), line: 372:2
CALBC1_12MHZ_ #define, value: (0x10FBu), line: 946:2 947:2
CALBC1_16MHZ_ #define, value: (0x10F9u), line: 942:2 943:2
CALBC1_1MHZ_ #define, value: (0x10FFu), line: 954:2 955:2
CALBC1_8MHZ_ #define, value: (0x10FDu), line: 950:2 951:2
CALDCO_12MHZ_ #define, value: (0x10FAu), line: 944:2 945:2
CALDCO_16MHZ_ #define, value: (0x10F8u), line: 940:2 941:2
CALDCO_1MHZ_ #define, value: (0x10FEu), line: 952:2 953:2
CALDCO_8MHZ_ #define, value: (0x10FCu), line: 948:2 949:2
CAON #define, value: (0x08), line: 375:2
CAOUT #define, value: (0x01), line: 386:2
CAP #define, value: (0x0100u), line: 604:2
CAPD0 #define, value: (0x01), line: 395:2
CAPD1 #define, value: (0x02), line: 396:2
CAPD2 #define, value: (0x04), line: 397:2
CAPD3 #define, value: (0x08), line: 398:2
CAPD4 #define, value: (0x10), line: 399:2
CAPD5 #define, value: (0x20), line: 400:2
CAPD6 #define, value: (0x40), line: 401:2
CAPD7 #define, value: (0x80), line: 402:2
CAPD_ #define, value: (0x005Bu), line: 369:2 370:2
CAREF0 #define, value: (0x10), line: 376:2
CAREF1 #define, value: (0x20), line: 377:2
CAREF_0 #define, value: (0x00), line: 381:2
CAREF_1 #define, value: (0x10), line: 382:2
CAREF_2 #define, value: (0x20), line: 383:2
CAREF_3 #define, value: (0x30), line: 384:2
CARSEL #define, value: (0x40), line: 378:2
CASHORT #define, value: (0x80), line: 393:2
CCI #define, value: (0x0008u), line: 609:2
CCIE #define, value: (0x0010u), line: 608:2
CCIFG #define, value: (0x0001u), line: 612:2
CCIS0 #define, value: (0x1000u), line: 601:2
CCIS1 #define, value: (0x2000u), line: 600:2
CCIS_0 #define, value: (0*0x1000u), line: 622:2
CCIS_1 #define, value: (1*0x1000u), line: 623:2
CCIS_2 #define, value: (2*0x1000u), line: 624:2
CCIS_3 #define, value: (3*0x1000u), line: 625:2
CCR0 #define, value: TACCR0, line: 565:2
CCR0_ #define, value: TACCR0_, line: 571:2
CCR1 #define, value: TACCR1, line: 566:2
CCR1_ #define, value: TACCR1_, line: 572:2
CCR2 #define, value: TACCR2, line: 567:2
CCR2_ #define, value: TACCR2_, line: 573:2
CCTL0 #define, value: TACCTL0, line: 562:2
CCTL0_ #define, value: TACCTL0_, line: 568:2
CCTL1 #define, value: TACCTL1, line: 563:2
CCTL1_ #define, value: TACCTL1_, line: 569:2
CCTL2 #define, value: TACCTL2, line: 564:2
CCTL2_ #define, value: TACCTL2_, line: 570:2
CM0 #define, value: (0x4000u), line: 599:2
CM1 #define, value: (0x8000u), line: 598:2
CM_0 #define, value: (0*0x4000u), line: 626:2
CM_1 #define, value: (1*0x4000u), line: 627:2
CM_2 #define, value: (2*0x4000u), line: 628:2
CM_3 #define, value: (3*0x4000u), line: 629:2
COMPARATORA_VECTOR #define, value: (11 * 2u), line: 971:2
CONSEQ0 #define, value: (0x0002u), line: 212:2
CONSEQ1 #define, value: (0x0004u), line: 213:2
CONSEQ_0 #define, value: (0*2u), line: 228:2
CONSEQ_1 #define, value: (1*2u), line: 229:2
CONSEQ_2 #define, value: (2*2u), line: 230:2
CONSEQ_3 #define, value: (3*2u), line: 231:2
COV #define, value: (0x0002u), line: 611:2
CPUOFF #define, value: (0x0010u), line: 83:2
DCO0 #define, value: (0x20), line: 295:2
DCO1 #define, value: (0x40), line: 296:2
DCO2 #define, value: (0x80), line: 297:2
DCOCTL_ #define, value: (0x0056u), line: 281:2 282:2
DEFC #define, line: 42:2 128:2 135:2 143:2 151:2
164:2 166:2 168:2 282:2
284:2 286:2 288:2 366:2
368:2 370:2 462:2 464:2
466:2 468:2 470:2 472:2
474:2 476:2 478:2 481:2
483:2 485:2 487:2 489:2
491:2 493:2 495:2 497:2
505:2 507:2 509:2 511:2
513:2 515:2 677:2 679:2
681:2 683:2 685:2 687:2
689:2 691:2 693:2 695:2
697:2 702:2 704:2 706:2
708:2 710:2 712:2 714:2
716:2 941:2 943:2 945:2
947:2 949:2 951:2 953:2
955:2
DEFW #define, line: 43:2 171:2 173:2 175:2 177:2
410:2 412:2 414:2 523:2
525:2 527:2 529:2 531:2
533:2 535:2 537:2 539:2
645:2 647:2 649:2 651:2
653:2 655:2 657:2 659:2
661:2 718:2 720:2 893:2
DIVA0 #define, value: (0x10), line: 303:2
DIVA1 #define, value: (0x20), line: 304:2
DIVA_0 #define, value: (0x00), line: 308:2
DIVA_1 #define, value: (0x10), line: 309:2
DIVA_2 #define, value: (0x20), line: 310:2
DIVA_3 #define, value: (0x30), line: 311:2
DIVM0 #define, value: (0x10), line: 316:2
DIVM1 #define, value: (0x20), line: 317:2
DIVM_0 #define, value: (0x00), line: 326:2
DIVM_1 #define, value: (0x10), line: 327:2
DIVM_2 #define, value: (0x20), line: 328:2
DIVM_3 #define, value: (0x30), line: 329:2
DIVS0 #define, value: (0x02), line: 313:2
DIVS1 #define, value: (0x04), line: 314:2
DIVS_0 #define, value: (0x00), line: 321:2
DIVS_1 #define, value: (0x02), line: 322:2
DIVS_2 #define, value: (0x04), line: 323:2
DIVS_3 #define, value: (0x06), line: 324:2
EMEX #define, value: (0x0020u), line: 451:2
ENC #define, value: (0x002), line: 181:2
ERASE #define, value: (0x0002u), line: 420:2
FAIL #define, value: (0x0080u), line: 453:2
FCTL1_ #define, value: (0x0128u), line: 409:2 410:2
FCTL2_ #define, value: (0x012Au), line: 411:2 412:2
FCTL3_ #define, value: (0x012Cu), line: 413:2 414:2
FLASHEND #define, value: (0xDFFF), line: 32:3
FLASHSTART #define, value: (0xC000), line: 31:3 41
FN0 #define, value: (0x0001u), line: 426:2
FN1 #define, value: (0x0002u), line: 427:2
FN2 #define, value: (0x0004u), line: 429:2
FN3 #define, value: (0x0008u), line: 432:2
FN4 #define, value: (0x0010u), line: 435:2
FN5 #define, value: (0x0020u), line: 437:2
FRKEY #define, value: (0x9600u), line: 416:2
FSSEL0 #define, value: (0x0040u), line: 438:2
FSSEL1 #define, value: (0x0080u), line: 439:2
FSSEL_0 #define, value: (0x0000u), line: 441:2
FSSEL_1 #define, value: (0x0040u), line: 442:2
FSSEL_2 #define, value: (0x0080u), line: 443:2
FSSEL_3 #define, value: (0x00C0u), line: 444:2
FWKEY #define, value: (0xA500u), line: 417:2
FXKEY #define, value: (0x3300u), line: 418:2
GIE #define, value: (0x0008u), line: 82:2
ID0 #define, value: (0x0040u), line: 578:2
ID1 #define, value: (0x0080u), line: 577:2
ID_0 #define, value: (0*0x40u), line: 589:2
ID_1 #define, value: (1*0x40u), line: 590:2
ID_2 #define, value: (2*0x40u), line: 591:2
ID_3 #define, value: (3*0x40u), line: 592:2
IE1_ #define, value: (0x0000u), line: 127:2 128:2
IE2_ #define, value: (0x0001u), line: 142:2 143:2
IFG1_ #define, value: (0x0002u), line: 134:2 135:2
IFG2_ #define, value: (0x0003u), line: 150:2 151:2
INCH0 #define, value: (0x1000u), line: 223:2
INCH1 #define, value: (0x2000u), line: 224:2
INCH2 #define, value: (0x4000u), line: 225:2
INCH3 #define, value: (0x8000u), line: 226:2
INCH_0 #define, value: (0*0x1000u), line: 252:2
INCH_1 #define, value: (1*0x1000u), line: 253:2
INCH_10 #define, value: (10*0x1000u), line: 262:2
INCH_11 #define, value: (11*0x1000u), line: 263:2
INCH_12 #define, value: (12*0x1000u), line: 264:2
INCH_13 #define, value: (13*0x1000u), line: 265:2
INCH_14 #define, value: (14*0x1000u), line: 266:2
INCH_15 #define, value: (15*0x1000u), line: 267:2
INCH_2 #define, value: (2*0x1000u), line: 254:2
INCH_3 #define, value: (3*0x1000u), line: 255:2
INCH_4 #define, value: (4*0x1000u), line: 256:2
INCH_5 #define, value: (5*0x1000u), line: 257:2
INCH_6 #define, value: (6*0x1000u), line: 258:2
INCH_7 #define, value: (7*0x1000u), line: 259:2
INCH_8 #define, value: (8*0x1000u), line: 260:2
INCH_9 #define, value: (9*0x1000u), line: 261:2
INDEX #define, value: R8, line: 46:3
INFOEND #define, value: (0x10FF), line: 28:3
INFOSEG #define, value: (128), line: 34:3
INFOSTART #define, value: (0x1000), line: 27:3
IP #define, value: R5, line: 41:3
IRACL #define, value: R12, line: 59:3
IRACM #define, value: R13, line: 60:3
IRBT #define, value: W, line: 61:3
IROP1 #define, value: TOS, line: 56:3
IROP2L #define, value: R10, line: 57:3
IROP2M #define, value: R11, line: 58:3
ISSH #define, value: (0x0100u), line: 219:2
KEYV #define, value: (0x0002u), line: 447:2
LFXT1OF #define, value: (0x01), line: 336:2
LFXT1S0 #define, value: (0x10), line: 340:2
LFXT1S1 #define, value: (0x20), line: 341:2
LFXT1S_0 #define, value: (0x00), line: 350:2
LFXT1S_1 #define, value: (0x10), line: 351:2
LFXT1S_2 #define, value: (0x20), line: 352:2
LFXT1S_3 #define, value: (0x30), line: 353:2
LIMIT #define, value: R9, line: 47:3
LOCK #define, value: (0x0010u), line: 450:2
LOCKA #define, value: (0x0040u), line: 452:2
LPM0 #define, value: (CPUOFF), line: 91:2
LPM1 #define, value: (SCG0+CPUOFF), line: 92:2
LPM2 #define, value: (SCG1+CPUOFF), line: 93:2
LPM3 #define, value: (SCG1+SCG0+CPUOFF), line: 94:2
LPM4 #define, value: (SCG1+SCG0+OSCOFF+CPUOFF), line: 95:2
MAINSEG #define, value: (512), line: 33:3
MC0 #define, value: (0x0010u), line: 580:2
MC1 #define, value: (0x0020u), line: 579:2
MC_0 #define, value: (0*0x10u), line: 585:2
MC_1 #define, value: (1*0x10u), line: 586:2
MC_2 #define, value: (2*0x10u), line: 587:2
MC_3 #define, value: (3*0x10u), line: 588:2
MERAS #define, value: (0x0004u), line: 421:2
MOD0 #define, value: (0x01), line: 290:2
MOD1 #define, value: (0x02), line: 291:2
MOD2 #define, value: (0x04), line: 292:2
MOD3 #define, value: (0x08), line: 293:2
MOD4 #define, value: (0x10), line: 294:2
MSC #define, value: (0x080), line: 187:2
N #define, value: (0x0004u), line: 80:2
NMIIE #define, value: (0x10), line: 131:2
NMIIFG #define, value: (0x10), line: 140:2
NMI_VECTOR #define, value: (14 * 2u), line: 974:2
OFIE #define, value: (0x02), line: 130:2
OFIFG #define, value: (0x02), line: 137:2
OSCOFF #define, value: (0x0020u), line: 84:2
OUT #define, value: (0x0004u), line: 610:2
OUTMOD0 #define, value: (0x0020u), line: 607:2
OUTMOD1 #define, value: (0x0040u), line: 606:2
OUTMOD2 #define, value: (0x0080u), line: 605:2
OUTMOD_0 #define, value: (0*0x20u), line: 614:2
OUTMOD_1 #define, value: (1*0x20u), line: 615:2
OUTMOD_2 #define, value: (2*0x20u), line: 616:2
OUTMOD_3 #define, value: (3*0x20u), line: 617:2
OUTMOD_4 #define, value: (4*0x20u), line: 618:2
OUTMOD_5 #define, value: (5*0x20u), line: 619:2
OUTMOD_6 #define, value: (6*0x20u), line: 620:2
OUTMOD_7 #define, value: (7*0x20u), line: 621:2
P1DIR_ #define, value: (0x0022u), line: 465:2 466:2
P1IES_ #define, value: (0x0024u), line: 469:2 470:2
P1IE_ #define, value: (0x0025u), line: 471:2 472:2
P1IFG_ #define, value: (0x0023u), line: 467:2 468:2
P1IN_ #define, value: (0x0020u), line: 461:2 462:2
P1OUT_ #define, value: (0x0021u), line: 463:2 464:2
P1REN_ #define, value: (0x0027u), line: 477:2 478:2
P1SEL2_ #define, value: (0x0041u), line: 475:2 476:2
P1SEL_ #define, value: (0x0026u), line: 473:2 474:2
P2CA0 #define, value: (0x04), line: 388:2
P2CA1 #define, value: (0x08), line: 389:2
P2CA2 #define, value: (0x10), line: 390:2
P2CA3 #define, value: (0x20), line: 391:2
P2CA4 #define, value: (0x40), line: 392:2
P2DIR_ #define, value: (0x002Au), line: 484:2 485:2
P2IES_ #define, value: (0x002Cu), line: 488:2 489:2
P2IE_ #define, value: (0x002Du), line: 490:2 491:2
P2IFG_ #define, value: (0x002Bu), line: 486:2 487:2
P2IN_ #define, value: (0x0028u), line: 480:2 481:2
P2OUT_ #define, value: (0x0029u), line: 482:2 483:2
P2REN_ #define, value: (0x002Fu), line: 496:2 497:2
P2SEL2_ #define, value: (0x0042u), line: 494:2 495:2
P2SEL_ #define, value: (0x002Eu), line: 492:2 493:2
P3DIR_ #define, value: (0x001Au), line: 508:2 509:2
P3IN_ #define, value: (0x0018u), line: 504:2 505:2
P3OUT_ #define, value: (0x0019u), line: 506:2 507:2
P3REN_ #define, value: (0x0010u), line: 514:2 515:2
P3SEL2_ #define, value: (0x0043u), line: 512:2 513:2
P3SEL_ #define, value: (0x001Bu), line: 510:2 511:2
PORIFG #define, value: (0x04), line: 138:2
PORT1_VECTOR #define, value: (2 * 2u), line: 963:2
PORT2_VECTOR #define, value: (3 * 2u), line: 964:2
PSP #define, value: R4, line: 40:3
Q #define, value: R12, line: 52:3
RAMEND #define, value: (0x03FF), line: 30:3
RAMSTART #define, value: (0x0200), line: 29:3
READ_ONLY #define, value: const, line: 50:2 462:2 481:2 505:2 523:2
645:2 689:2 714:2 941:2
943:2 945:2 947:2 949:2
951:2 953:2 955:2
REF2_5V #define, value: (0x040), line: 186:2
REFBURST #define, value: (0x100), line: 188:2
REFON #define, value: (0x020), line: 185:2
REFOUT #define, value: (0x200), line: 189:2
RESET_VECTOR #define, value: (15 * 2u), line: 975:2
RSEL0 #define, value: (0x01), line: 299:2
RSEL1 #define, value: (0x02), line: 300:2
RSEL2 #define, value: (0x04), line: 301:2
RSEL3 #define, value: (0x08), line: 302:2
RSP #define, value: SP, line: 39:3
RSTIFG #define, value: (0x08), line: 139:2
SCCI #define, value: (0x0400u), line: 603:2
SCG0 #define, value: (0x0040u), line: 85:2
SCG1 #define, value: (0x0080u), line: 86:2
SCS #define, value: (0x0800u), line: 602:2
SEGWRT #define, value: (0x0080u), line: 424:2
SELM0 #define, value: (0x40), line: 318:2
SELM1 #define, value: (0x80), line: 319:2
SELM_0 #define, value: (0x00), line: 331:2
SELM_1 #define, value: (0x40), line: 332:2
SELM_2 #define, value: (0x80), line: 333:2
SELM_3 #define, value: (0xC0), line: 334:2
SELS #define, value: (0x08), line: 315:2
SHS0 #define, value: (0x0400u), line: 221:2
SHS1 #define, value: (0x0800u), line: 222:2
SHS_0 #define, value: (0*0x400u), line: 247:2
SHS_1 #define, value: (1*0x400u), line: 248:2
SHS_2 #define, value: (2*0x400u), line: 249:2
SHS_3 #define, value: (3*0x400u), line: 250:2
SREF0 #define, value: (0x2000u), line: 193:2
SREF1 #define, value: (0x4000u), line: 194:2
SREF2 #define, value: (0x8000u), line: 195:2
SREF_0 #define, value: (0*0x2000u), line: 201:2
SREF_1 #define, value: (1*0x2000u), line: 202:2
SREF_2 #define, value: (2*0x2000u), line: 203:2
SREF_3 #define, value: (3*0x2000u), line: 204:2
SREF_4 #define, value: (4*0x2000u), line: 205:2
SREF_5 #define, value: (5*0x2000u), line: 206:2
SREF_6 #define, value: (6*0x2000u), line: 207:2
SREF_7 #define, value: (7*0x2000u), line: 208:2
T #define, value: R13, line: 53:3
TA0CCR0_ #define, value: (0x0172u), line: 534:2 535:2
TA0CCR1_ #define, value: (0x0174u), line: 536:2 537:2
TA0CCR2_ #define, value: (0x0176u), line: 538:2 539:2
TA0CCTL0_ #define, value: (0x0162u), line: 526:2 527:2
TA0CCTL1_ #define, value: (0x0164u), line: 528:2 529:2
TA0CCTL2_ #define, value: (0x0166u), line: 530:2 531:2
TA0CTL_ #define, value: (0x0160u), line: 524:2 525:2
TA0IV_ #define, value: (0x012Eu), line: 522:2 523:2
TA0IV_6 #define, value: (0x0006u), line: 635:2
TA0IV_8 #define, value: (0x0008u), line: 636:2
TA0IV_NONE #define, value: (0x0000u), line: 632:2
TA0IV_TACCR1 #define, value: (0x0002u), line: 633:2
TA0IV_TACCR2 #define, value: (0x0004u), line: 634:2
TA0IV_TAIFG #define, value: (0x000Au), line: 637:2
TA0R_ #define, value: (0x0170u), line: 532:2 533:2
TA1CCR0_ #define, value: (0x0192u), line: 656:2 657:2
TA1CCR1_ #define, value: (0x0194u), line: 658:2 659:2
TA1CCR2_ #define, value: (0x0196u), line: 660:2 661:2
TA1CCTL0_ #define, value: (0x0182u), line: 648:2 649:2
TA1CCTL1_ #define, value: (0x0184u), line: 650:2 651:2
TA1CCTL2_ #define, value: (0x0186u), line: 652:2 653:2
TA1CTL_ #define, value: (0x0180u), line: 646:2 647:2
TA1IV_ #define, value: (0x011Eu), line: 644:2 645:2
TA1IV_NONE #define, value: (0x0000u), line: 666:2
TA1IV_TACCR1 #define, value: (0x0002u), line: 667:2
TA1IV_TACCR2 #define, value: (0x0004u), line: 668:2
TA1IV_TAIFG #define, value: (0x000Au), line: 669:2
TA1R_ #define, value: (0x0190u), line: 654:2 655:2
TACCR0 #define, value: TA0CCR0, line: 548:2
TACCR0_ #define, value: TA0CCR0_, line: 557:2
TACCR1 #define, value: TA0CCR1, line: 549:2
TACCR1_ #define, value: TA0CCR1_, line: 558:2
TACCR2 #define, value: TA0CCR2, line: 550:2
TACCR2_ #define, value: TA0CCR2_, line: 559:2
TACCTL0 #define, value: TA0CCTL0, line: 544:2
TACCTL0_ #define, value: TA0CCTL0_, line: 553:2
TACCTL1 #define, value: TA0CCTL1, line: 545:2
TACCTL1_ #define, value: TA0CCTL1_, line: 554:2
TACCTL2 #define, value: TA0CCTL2, line: 546:2
TACCTL2_ #define, value: TA0CCTL2_, line: 555:2
TACLR #define, value: (0x0004u), line: 581:2
TACTL #define, value: TA0CTL, line: 543:2
TACTL_ #define, value: TA0CTL_, line: 552:2
TAIE #define, value: (0x0002u), line: 582:2
TAIFG #define, value: (0x0001u), line: 583:2
TAIV #define, value: TA0IV, line: 542:2
TAIV_ #define, value: TA0IV_, line: 551:2
TAR #define, value: TA0R, line: 547:2
TAR_ #define, value: TA0R_, line: 556:2
TASSEL0 #define, value: (0x0100u), line: 576:2
TASSEL1 #define, value: (0x0200u), line: 575:2
TASSEL_0 #define, value: (0*0x100u), line: 593:2
TASSEL_1 #define, value: (1*0x100u), line: 594:2
TASSEL_2 #define, value: (2*0x100u), line: 595:2
TASSEL_3 #define, value: (3*0x100u), line: 596:2
TIMER0_A0_VECTOR #define, value: (9 * 2u), line: 969:2
TIMER0_A1_VECTOR #define, value: (8 * 2u), line: 968:2
TIMER1_A0_VECTOR #define, value: (13 * 2u), line: 973:2
TIMER1_A1_VECTOR #define, value: (12 * 2u), line: 972:2
TOS #define, value: R7, line: 43:3
UC0IE #define, value: IE2, line: 144:2
UC0IFG #define, value: IFG2, line: 152:2
UC7BIT #define, value: (0x10), line: 726:2
UCA0ABCTL_ #define, value: (0x005Du), line: 692:2 693:2
UCA0BR0_ #define, value: (0x0062u), line: 680:2 681:2
UCA0BR1_ #define, value: (0x0063u), line: 682:2 683:2
UCA0CTL0_ #define, value: (0x0060u), line: 676:2 677:2
UCA0CTL1_ #define, value: (0x0061u), line: 678:2 679:2
UCA0IRRCTL_ #define, value: (0x005Fu), line: 696:2 697:2
UCA0IRTCTL_ #define, value: (0x005Eu), line: 694:2 695:2
UCA0MCTL_ #define, value: (0x0064u), line: 684:2 685:2
UCA0RXBUF_ #define, value: (0x0066u), line: 688:2 689:2
UCA0RXIE #define, value: (0x01), line: 145:2
UCA0RXIFG #define, value: (0x01), line: 153:2
UCA0STAT_ #define, value: (0x0065u), line: 686:2 687:2
UCA0TXBUF_ #define, value: (0x0067u), line: 690:2 691:2
UCA0TXIE #define, value: (0x02), line: 146:2
UCA0TXIFG #define, value: (0x02), line: 154:2
UCA10 #define, value: (0x80), line: 738:2
UCABDEN #define, value: (0x01), line: 862:2
UCADDR #define, value: (0x02), line: 816:2
UCALIE #define, value: (0x01), line: 827:2
UCALIFG #define, value: (0x01), line: 835:2
UCB0BR0_ #define, value: (0x006Au), line: 705:2 706:2
UCB0BR1_ #define, value: (0x006Bu), line: 707:2 708:2
UCB0CTL0_ #define, value: (0x0068u), line: 701:2 702:2
UCB0CTL1_ #define, value: (0x0069u), line: 703:2 704:2
UCB0I2CIE_ #define, value: (0x006Cu), line: 709:2 710:2
UCB0I2COA_ #define, value: (0x0118u), line: 717:2 718:2
UCB0I2CSA_ #define, value: (0x011Au), line: 719:2 720:2
UCB0RXBUF_ #define, value: (0x006Eu), line: 713:2 714:2
UCB0RXIE #define, value: (0x04), line: 147:2
UCB0RXIFG #define, value: (0x04), line: 155:2
UCB0STAT_ #define, value: (0x006Du), line: 711:2 712:2
UCB0TXBUF_ #define, value: (0x006Fu), line: 715:2 716:2
UCB0TXIE #define, value: (0x08), line: 148:2
UCB0TXIFG #define, value: (0x08), line: 156:2
UCBBUSY #define, value: (0x10), line: 831:2
UCBRF0 #define, value: (0x10), line: 778:2
UCBRF1 #define, value: (0x20), line: 777:2
UCBRF2 #define, value: (0x40), line: 776:2
UCBRF3 #define, value: (0x80), line: 775:2
UCBRF_0 #define, value: (0x00), line: 784:2
UCBRF_1 #define, value: (0x10), line: 785:2
UCBRF_10 #define, value: (0xA0), line: 794:2
UCBRF_11 #define, value: (0xB0), line: 795:2
UCBRF_12 #define, value: (0xC0), line: 796:2
UCBRF_13 #define, value: (0xD0), line: 797:2
UCBRF_14 #define, value: (0xE0), line: 798:2
UCBRF_15 #define, value: (0xF0), line: 799:2
UCBRF_2 #define, value: (0x20), line: 786:2
UCBRF_3 #define, value: (0x30), line: 787:2
UCBRF_4 #define, value: (0x40), line: 788:2
UCBRF_5 #define, value: (0x50), line: 789:2
UCBRF_6 #define, value: (0x60), line: 790:2
UCBRF_7 #define, value: (0x70), line: 791:2
UCBRF_8 #define, value: (0x80), line: 792:2
UCBRF_9 #define, value: (0x90), line: 793:2
UCBRK #define, value: (0x08), line: 814:2
UCBRKIE #define, value: (0x10), line: 751:2
UCBRS0 #define, value: (0x02), line: 781:2
UCBRS1 #define, value: (0x04), line: 780:2
UCBRS2 #define, value: (0x08), line: 779:2
UCBRS_0 #define, value: (0x00), line: 801:2
UCBRS_1 #define, value: (0x02), line: 802:2
UCBRS_2 #define, value: (0x04), line: 803:2
UCBRS_3 #define, value: (0x06), line: 804:2
UCBRS_4 #define, value: (0x08), line: 805:2
UCBRS_5 #define, value: (0x0A), line: 806:2
UCBRS_6 #define, value: (0x0C), line: 807:2
UCBRS_7 #define, value: (0x0E), line: 808:2
UCBTOE #define, value: (0x04), line: 860:2
UCBUSY #define, value: (0x01), line: 817:2
UCCKPH #define, value: (0x80), line: 733:2
UCCKPL #define, value: (0x40), line: 734:2
UCDELIM0 #define, value: (0x10), line: 858:2
UCDELIM1 #define, value: (0x20), line: 857:2
UCDORM #define, value: (0x08), line: 752:2
UCFE #define, value: (0x40), line: 811:2
UCGC #define, value: (0x20), line: 830:2
UCGCEN #define, value: (0x8000u), line: 864:2
UCIDLE #define, value: (0x02), line: 818:2
UCIREN #define, value: (0x01), line: 844:2
UCIRRXFE #define, value: (0x01), line: 853:2
UCIRRXFL0 #define, value: (0x04), line: 851:2
UCIRRXFL1 #define, value: (0x08), line: 850:2
UCIRRXFL2 #define, value: (0x10), line: 849:2
UCIRRXFL3 #define, value: (0x20), line: 848:2
UCIRRXFL4 #define, value: (0x40), line: 847:2
UCIRRXFL5 #define, value: (0x80), line: 846:2
UCIRRXPL #define, value: (0x02), line: 852:2
UCIRTXCLK #define, value: (0x02), line: 843:2
UCIRTXPL0 #define, value: (0x04), line: 842:2
UCIRTXPL1 #define, value: (0x08), line: 841:2
UCIRTXPL2 #define, value: (0x10), line: 840:2
UCIRTXPL3 #define, value: (0x20), line: 839:2
UCIRTXPL4 #define, value: (0x40), line: 838:2
UCIRTXPL5 #define, value: (0x80), line: 837:2
UCLISTEN #define, value: (0x80), line: 810:2
UCMM #define, value: (0x20), line: 740:2
UCMODE0 #define, value: (0x02), line: 729:2
UCMODE1 #define, value: (0x04), line: 728:2
UCMODE_0 #define, value: (0x00), line: 742:2
UCMODE_1 #define, value: (0x02), line: 743:2
UCMODE_2 #define, value: (0x04), line: 744:2
UCMODE_3 #define, value: (0x06), line: 745:2
UCMSB #define, value: (0x20), line: 725:2
UCMST #define, value: (0x08), line: 735:2
UCNACKIE #define, value: (0x08), line: 824:2
UCNACKIFG #define, value: (0x08), line: 832:2
UCOA0 #define, value: (0x0001u), line: 874:2
UCOA1 #define, value: (0x0002u), line: 873:2
UCOA2 #define, value: (0x0004u), line: 872:2
UCOA3 #define, value: (0x0008u), line: 871:2
UCOA4 #define, value: (0x0010u), line: 870:2
UCOA5 #define, value: (0x0020u), line: 869:2
UCOA6 #define, value: (0x0040u), line: 868:2
UCOA7 #define, value: (0x0080u), line: 867:2
UCOA8 #define, value: (0x0100u), line: 866:2
UCOA9 #define, value: (0x0200u), line: 865:2
UCOE #define, value: (0x20), line: 812:2
UCOS16 #define, value: (0x01), line: 782:2
UCPAR #define, value: (0x40), line: 724:2
UCPE #define, value: (0x10), line: 813:2
UCPEN #define, value: (0x80), line: 723:2
UCRXEIE #define, value: (0x20), line: 750:2
UCRXERR #define, value: (0x04), line: 815:2
UCSA0 #define, value: (0x0001u), line: 885:2
UCSA1 #define, value: (0x0002u), line: 884:2
UCSA2 #define, value: (0x0004u), line: 883:2
UCSA3 #define, value: (0x0008u), line: 882:2
UCSA4 #define, value: (0x0010u), line: 881:2
UCSA5 #define, value: (0x0020u), line: 880:2
UCSA6 #define, value: (0x0040u), line: 879:2
UCSA7 #define, value: (0x0080u), line: 878:2
UCSA8 #define, value: (0x0100u), line: 877:2
UCSA9 #define, value: (0x0200u), line: 876:2
UCSCLLOW #define, value: (0x40), line: 829:2
UCSLA10 #define, value: (0x40), line: 739:2
UCSPB #define, value: (0x08), line: 727:2
UCSSEL0 #define, value: (0x40), line: 749:2
UCSSEL1 #define, value: (0x80), line: 748:2
UCSSEL_0 #define, value: (0x00), line: 770:2
UCSSEL_1 #define, value: (0x40), line: 771:2
UCSSEL_2 #define, value: (0x80), line: 772:2
UCSSEL_3 #define, value: (0xC0), line: 773:2
UCSTOE #define, value: (0x08), line: 859:2
UCSTPIE #define, value: (0x04), line: 825:2
UCSTPIFG #define, value: (0x04), line: 833:2
UCSTTIE #define, value: (0x02), line: 826:2
UCSTTIFG #define, value: (0x02), line: 834:2
UCSWRST #define, value: (0x01), line: 755:2
UCSYNC #define, value: (0x01), line: 730:2
UCTR #define, value: (0x10), line: 766:2
UCTXADDR #define, value: (0x04), line: 753:2
UCTXBRK #define, value: (0x02), line: 754:2
UCTXNACK #define, value: (0x08), line: 767:2
UCTXSTP #define, value: (0x04), line: 768:2
UCTXSTT #define, value: (0x02), line: 769:2
USCIAB0RX_VECTOR #define, value: (7 * 2u), line: 967:2
USCIAB0TX_VECTOR #define, value: (6 * 2u), line: 966:2
V #define, value: (0x0100u), line: 81:2
W #define, value: R6, line: 42:3
WAIT #define, value: (0x0008u), line: 449:2
WDTCNTCL #define, value: (0x0008u), line: 898:2
WDTCTL_ #define, value: (0x0120u), line: 892:2 893:2
WDTHOLD #define, value: (0x0080u), line: 902:2
WDTIE #define, value: (0x01), line: 129:2
WDTIFG #define, value: (0x01), line: 136:2
WDTIS0 #define, value: (0x0001u), line: 895:2
WDTIS1 #define, value: (0x0002u), line: 896:2
WDTNMI #define, value: (0x0020u), line: 900:2
WDTNMIES #define, value: (0x0040u), line: 901:2
WDTPW #define, value: (0x5A00u), line: 904:2
WDTSSEL #define, value: (0x0004u), line: 897:2
WDTTMSEL #define, value: (0x0010u), line: 899:2
WDT_ADLY_1000 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL), line: 913:2
WDT_ADLY_16 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1), line: 915:2
WDT_ADLY_1_9 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0), line: 916:2
WDT_ADLY_250 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0), line: 914:2
WDT_ARST_1000 #define, value: (WDTPW+WDTCNTCL+WDTSSEL), line: 924:2
WDT_ARST_16 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1), line: 926:2
WDT_ARST_1_9 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0), line: 927:2
WDT_ARST_250 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0), line: 925:2
WDT_MDLY_0_064 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0), line: 911:2
WDT_MDLY_0_5 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1), line: 910:2
WDT_MDLY_32 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL), line: 908:2
WDT_MDLY_8 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0), line: 909:2
WDT_MRST_0_064 #define, value: (WDTPW+WDTCNTCL+WDTIS1+WDTIS0), line: 922:2
WDT_MRST_0_5 #define, value: (WDTPW+WDTCNTCL+WDTIS1), line: 921:2
WDT_MRST_32 #define, value: (WDTPW+WDTCNTCL), line: 919:2
WDT_MRST_8 #define, value: (WDTPW+WDTCNTCL+WDTIS0), line: 920:2
WDT_VECTOR #define, value: (10 * 2u), line: 970:2
WRT #define, value: (0x0040u), line: 422:2
X #define, value: R10, line: 50:3
XCAP0 #define, value: (0x04), line: 338:2
XCAP1 #define, value: (0x08), line: 339:2
XCAP_0 #define, value: (0x00), line: 345:2
XCAP_1 #define, value: (0x04), line: 346:2
XCAP_2 #define, value: (0x08), line: 347:2
XCAP_3 #define, value: (0x0C), line: 348:2
XT2OF #define, value: (0x02), line: 337:2
XT2OFF #define, value: (0x80), line: 306:2
XT2S0 #define, value: (0x40), line: 342:2
XT2S1 #define, value: (0x80), line: 343:2
XT2S_0 #define, value: (0x00), line: 355:2
XT2S_1 #define, value: (0x40), line: 356:2
XT2S_2 #define, value: (0x80), line: 357:2
XT2S_3 #define, value: (0xC0), line: 358:2
XTS #define, value: (0x40), line: 305:2
Y #define, value: R11, line: 51:3
Z #define, value: (0x0002u), line: 79:2
__430X_CORE__ #define, value: 1, line: 0
__430_CORE__ #define, value: 0, line: 0
__A430__ #define, value: 1, line: 0
__BUILD_NUMBER__ #define, line: 0
__CORE__ #define, value: 0, line: 0
__DATE__ #define, line: 0
__FILE__ #define, line: 0
__IAR_SYSTEMS_ASM #define, line: 0
__IAR_SYSTEMS_ASM__ #define, line: 0
__LINE__ #define, line: 0
__MSP430G2553 #define, value: , line: 16:2
__MSP430G2553__ #define, value: 1, line: 0
__MSP430_HAS_ADC10__ #define, value: , line: 161:2
__MSP430_HAS_BC2__ #define, value: , line: 279:2
__MSP430_HAS_CAPLUS__ #define, value: , line: 363:2
__MSP430_HAS_FLASH2__ #define, value: , line: 407:2
__MSP430_HAS_PORT1_R__ #define, value: , line: 458:2
__MSP430_HAS_PORT2_R__ #define, value: , line: 459:2
__MSP430_HAS_PORT3_R__ #define, value: , line: 502:2
__MSP430_HAS_T1A3__ #define, value: , line: 642:2
__MSP430_HAS_TA3__ #define, value: , line: 520:2
__MSP430_HAS_USCI__ #define, value: , line: 674:2
__MSP430_HAS_WDT__ #define, value: , line: 890:2
__SUBVERSION__ #define, line: 0
__TID__ #define, line: 0 24:2
__TIME__ #define, line: 0
__VER__ #define, line: 0
__msp430 #define, value: , line: 9:1
Segment Type Mode
----------------------------------------
INFOB UNTYPED REL
Label Mode Type Segment Value/Offset
------------------------------------------------------------------------------
ADC10AE0 ABS CONST UNTYP. ASEG 4A
ADC10CTL0 ABS CONST UNTYP. ASEG 1B0
ADC10CTL1 ABS CONST UNTYP. ASEG 1B2
ADC10DTC0 ABS CONST UNTYP. ASEG 48
ADC10DTC1 ABS CONST UNTYP. ASEG 49
ADC10MEM ABS CONST UNTYP. ASEG 1B4
ADC10SA ABS CONST UNTYP. ASEG 1BC
AppU0 REL CONST PUB UNTYP. INFOB 2
BCSCTL1 ABS CONST UNTYP. ASEG 57
BCSCTL2 ABS CONST UNTYP. ASEG 58
BCSCTL3 ABS CONST UNTYP. ASEG 53
CACTL1 ABS CONST UNTYP. ASEG 59
CACTL2 ABS CONST UNTYP. ASEG 5A
CALBC1_12MHZ ABS CONST UNTYP. ASEG 10FB
CALBC1_16MHZ ABS CONST UNTYP. ASEG 10F9
CALBC1_1MHZ ABS CONST UNTYP. ASEG 10FF
CALBC1_8MHZ ABS CONST UNTYP. ASEG 10FD
CALDCO_12MHZ ABS CONST UNTYP. ASEG 10FA
CALDCO_16MHZ ABS CONST UNTYP. ASEG 10F8
CALDCO_1MHZ ABS CONST UNTYP. ASEG 10FE
CALDCO_8MHZ ABS CONST UNTYP. ASEG 10FC
CAPD ABS CONST UNTYP. ASEG 5B
DCOCTL ABS CONST UNTYP. ASEG 56
DOTCOLD ABS CONST EXT [002] UNTYP. __EXTERNS Solved Extern
FCTL1 ABS CONST UNTYP. ASEG 128
FCTL2 ABS CONST UNTYP. ASEG 12A
FCTL3 ABS CONST UNTYP. ASEG 12C
IE1 ABS CONST UNTYP. ASEG 0
IE2 ABS CONST UNTYP. ASEG 1
IFG1 ABS CONST UNTYP. ASEG 2
IFG2 ABS CONST UNTYP. ASEG 3
NOOP ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern
P1DIR ABS CONST UNTYP. ASEG 22
P1IE ABS CONST UNTYP. ASEG 25
P1IES ABS CONST UNTYP. ASEG 24
P1IFG ABS CONST UNTYP. ASEG 23
P1IN ABS CONST UNTYP. ASEG 20
P1OUT ABS CONST UNTYP. ASEG 21
P1REN ABS CONST UNTYP. ASEG 27
P1SEL ABS CONST UNTYP. ASEG 26
P1SEL2 ABS CONST UNTYP. ASEG 41
P2DIR ABS CONST UNTYP. ASEG 2A
P2IE ABS CONST UNTYP. ASEG 2D
P2IES ABS CONST UNTYP. ASEG 2C
P2IFG ABS CONST UNTYP. ASEG 2B
P2IN ABS CONST UNTYP. ASEG 28
P2OUT ABS CONST UNTYP. ASEG 29
P2REN ABS CONST UNTYP. ASEG 2F
P2SEL ABS CONST UNTYP. ASEG 2E
P2SEL2 ABS CONST UNTYP. ASEG 42
P3DIR ABS CONST UNTYP. ASEG 1A
P3IN ABS CONST UNTYP. ASEG 18
P3OUT ABS CONST UNTYP. ASEG 19
P3REN ABS CONST UNTYP. ASEG 10
P3SEL ABS CONST UNTYP. ASEG 1B
P3SEL2 ABS CONST UNTYP. ASEG 43
RAMDICT ABS CONST EXT [000] UNTYP. __EXTERNS Solved Extern
TA0CCR0 ABS CONST UNTYP. ASEG 172
TA0CCR1 ABS CONST UNTYP. ASEG 174
TA0CCR2 ABS CONST UNTYP. ASEG 176
TA0CCTL0 ABS CONST UNTYP. ASEG 162
TA0CCTL1 ABS CONST UNTYP. ASEG 164
TA0CCTL2 ABS CONST UNTYP. ASEG 166
TA0CTL ABS CONST UNTYP. ASEG 160
TA0IV ABS CONST UNTYP. ASEG 12E
TA0R ABS CONST UNTYP. ASEG 170
TA1CCR0 ABS CONST UNTYP. ASEG 192
TA1CCR1 ABS CONST UNTYP. ASEG 194
TA1CCR2 ABS CONST UNTYP. ASEG 196
TA1CCTL0 ABS CONST UNTYP. ASEG 182
TA1CCTL1 ABS CONST UNTYP. ASEG 184
TA1CCTL2 ABS CONST UNTYP. ASEG 186
TA1CTL ABS CONST UNTYP. ASEG 180
TA1IV ABS CONST UNTYP. ASEG 11E
TA1R ABS CONST UNTYP. ASEG 190
UCA0ABCTL ABS CONST UNTYP. ASEG 5D
UCA0BR0 ABS CONST UNTYP. ASEG 62
UCA0BR1 ABS CONST UNTYP. ASEG 63
UCA0CTL0 ABS CONST UNTYP. ASEG 60
UCA0CTL1 ABS CONST UNTYP. ASEG 61
UCA0IRRCTL ABS CONST UNTYP. ASEG 5F
UCA0IRTCTL ABS CONST UNTYP. ASEG 5E
UCA0MCTL ABS CONST UNTYP. ASEG 64
UCA0RXBUF ABS CONST UNTYP. ASEG 66
UCA0STAT ABS CONST UNTYP. ASEG 65
UCA0TXBUF ABS CONST UNTYP. ASEG 67
UCB0BR0 ABS CONST UNTYP. ASEG 6A
UCB0BR1 ABS CONST UNTYP. ASEG 6B
UCB0CTL0 ABS CONST UNTYP. ASEG 68
UCB0CTL1 ABS CONST UNTYP. ASEG 69
UCB0I2CIE ABS CONST UNTYP. ASEG 6C
UCB0I2COA ABS CONST UNTYP. ASEG 118
UCB0I2CSA ABS CONST UNTYP. ASEG 11A
UCB0RXBUF ABS CONST UNTYP. ASEG 6E
UCB0STAT ABS CONST UNTYP. ASEG 6D
UCB0TXBUF ABS CONST UNTYP. ASEG 6F
WDTCTL ABS CONST UNTYP. ASEG 120
__MSP430G2203__ ABS CONST UNTYP. ASEG Not solved
crcval REL CONST PUB UNTYP. INFOB 0
infoB REL CONST PUB UNTYP. INFOB 0
lastword ABS CONST EXT [001] UNTYP. __EXTERNS Solved Extern
##############################
# CRC:43C4 #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 34 #
##############################